Mixed-Signal Z183
Driven to Design 2000 Contest

Ended January 15, 2001 — Click here to visit the winners!

Conquer your toughest design challenges
with the Mixed-Signal Z183

All core hardware must be ZiLOG Z180-based.
(Eligible Parts: Z8S180, Z8L180, Z80182, Z8L182, Z80S183, and Z80L183)

Winning entries using the Z183 will receive an additional $500.

Register with Zilog for your FREE "Driven to Design Contest Pak". The contest Pak includes a free complimentary Mixed-Signal Z183 component sample, data sheets, contest rules, and entry form.

High performance

  • Speeds up to 33 MHz
  • 2 DMA channels
  • 2 enhanced UARTs

    Low-power operation

  • 5V and 3.3V
  • Low-power PLL oscillator
  • Low-current consumption sleep modes
  •  

    Flexibility

  • 2 16-bit timers
  • CSIO
  • 10-bit D/A converter
  • 8-channel 10-bit A/D at 500 Ksps
  • 8-bit programmable output generator
  • 2K SRAM
  • 1 Mbyte address capability
  • 32-bits GPIO
  • 1K Boot ROM with program included
  • Register with Zilog for your FREE "Driven to Design Contest Pak". The contest Pak includes a free complimentary Mixed-Signal Z183 component sample, data sheets, contest rules, and entry form.


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