Your entry to the WIZnet iEthernet
Design Contest 2007 must use at least one WIZnet W5100 (fully hardwired TCP/IP)
chip or iEthernet board/module that contains the
W5100. Any commercially available CPU is eligible for use in conjunction with
the W5100.
For
more information about the W5100, visit http://www.wiznet.co.kr/pro_iin_W5100.htm
In addition, all WIZnet iEthernet Design Contest 2007 winners will receive international recognition for their achievements. Circuit Cellar magazine will host the most noteworthy projects online in an expanded winners presentation.
Performance Benefits |
Line-speed data transmission
by hardwired logic
Up to 25Mbps throughput at application layer |
Implementation Benefits |
Easy & simple control
like memory
Save developing time and area |
Cost Benefits |
Easy TCP/IP implementation
without OS
MAC & PHY embedded |
Application Benefits |
Brand-New Hybrid
architecture supporting Hardwired & S/W TCP/IP
Support standard MII Interface in order to Interface the switch chip
having more than two Ethernet PHYs |
 Support Hardwired TCP/IP Protocols : TCP, UDP, ICMP, IPv4 ARP, IGMP, PPPoE
10BaseT/100BaseTX Ethernet MAC/PHY embedded
Support Auto Negotiation (Full-duplex and half duplex)
Support Auto MDI/MDIX
Support ADSL connection (with support PPPoE Protocol with PAP/CHAP Authentication mode)
Support 4 independent sockets simultaneously
Internal 16Kbytes Memory for Tx/Rx Buffers
0.18 μm CMOS technology
3.3V operation with 5V I/O signal tolerance
Small 80 Pin LQFP Package
Lead-Free Package
Support Direct and Indirect BUS interface
Support Serial Peripheral Interface(SPI MODE 0, 3)
Support MII Interface
Multi-function LED outputs (TX, RX, Full/Half duplex, Collision, Link, Speed)
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