A low-power, flash-memory MCU from Texas Instruments? That was enough to catch Tom’s attention. Despite a few skeletons in the closet, TI looks like it may be ready to jump into the MCU field.

There can be little doubt that Texas Instruments is an outfit deserving of a prominent spot in the IC Hall of Fame. In fact, TI’s Jack Kilby just received a Nobel prize in Physics (well deserved, I say) for his pioneering work. But, don’t forget TI also wrote the bible on TTL, long shouldered the American memory chip flag, and drove the DSP concept beyond its rocket science roots and into the heart of main street products.

Then there’s the parade of pioneering consumer products—from calculators, to digital watches, to toys like the good old Speak & Spell.

Of course, every successful company has skeletons in its closet. The question for companies that have never had any problems is, just how gracefully will they handle the inevitable arrival of the first rattling visitor? Successful outfits know when it’s time to put a product in the closet, how to keep it there until it’s laid to rest for good, or in rare cases, bring it back to life. "Hi, I’m TI-99/4" is the name tag on TI’s chief closet dweller.

Old-timers will recall the heyday (before IBM changed the rules) when anyone with a garage, soldering iron, and credit card could enter the PC biz. Quite a few companies gave it a whirl, as TI did with its TI-99/4, which was introduced with fanfare in June 1979 (see Photo 1).

Photo 1—Even with a full quiver of sidecar expansion options, the TI 99/4 became one of the here-today-gone-tomorrow casualties of the pre-IBM personal computer free-for-all.

Despite (or perhaps as a result of) TI’s heritage with calculators and such, their computer foray was rather rocky. The ’99/4 lived fast, died young, and left some 2.5 million good looking corpses. During my research for this story, I was surprised to discover that there’s still an active community of ’99/4 diehards out there (www.99er.net is a good site to get you headed in the right direction).

’99ers recall the day of reckoning in June 1983 when the ’99/4 was axed as Black Friday. Not that TI, Atari, Commodore, Coleco, Exidy, et al had a chance when IBM weighed in, but they were still dark days for the folks in Dallas.

You may ask, "What the heck does some old war story mean for designers today?"

Baby and Bath

Much like the PC biz, the MPU/MCU market was wide open at the time. Unlike today’s domination by a few large players and architectures, there were dozens of microchip wannabes jockeying for position.

Few may recall TI’s TMS 9900 chip (here’s the connection) that served as the brains for the ’99/4. Developed in 1975, it was actually quite advanced, a true 16-bit processor for its time (see Photo 2). Although it had an interesting design, the TMS 9900 pretty much went down with the ’99/4 ship.

Photo 2—In the early ’80s, two bytes may have been better than one, but still not enough for TMS 9900 to make a dent in the MCU market. Nice collar, dude!

Even though I’m sure there’s more to it, I can’t help but connect the dashing of its computer pretensions with the fact that TI never became a major factor in the mainstream MPU/MCU business. TI has sold a fair number of micros (including 4- and 8-bits), but it has yet to rise beyond the "other" column in market stats. TI can rely on a few huge OEM customers to keep the lights on, but hasn’t had much in the way of MPUs and MCUs ("Er, could I interest you in a DSP?") to offer the average designer on the street.

All right, enough nostalgia. Fast forward to the present.

Flipping restlessly through the pile of press kits from the recent Embedded Systems Conference, I almost blew right past the TI stuff. I thought it would probably tout yet another DSP, or perhaps a new and improved op-amp (recalling that TI recently acquired Burr-Brown).

I did a double take and paused in mid-toss to take a closer look….

"Low-Power Flash MCUs from Texas Instruments Available for Only $0.99."

My, my, what have we here?

They’re Back

My PR radar missed it, but apparently TI has been mobilizing for a major MCU push with the MSP430 family, most recently with the low-cost, flash memory-based MSP430F11x variants described in the press release. There are higher-end parts with lots of memory and peripherals, but it’s the small (20-pin), inexpensive flash memory ’F11x I find most intriguing (see Figure 1).

Figure 1—The ’F11x is real simple and, at under a buck in volume, real sweet.

Now the ’F11x lineup consists of four chips—’F110, ’F112, ’F1101, and ’F1121. The amount of onboard memory is the difference between the ’110 and ’112; the former having 1-KB and 128-byte flash memory and 128-byte RAM and the latter sporting 4-KB and 256-byte flash memory and 256-byte RAM. The ’F11x1 versions add an analog comparator.

Figure 1 looks rather typical, yet understates the capabilities and unique features of the part.

Consider the flash memory. Rather than having a single monolithic array, it’s comprised of 512-byte main memory segments and 128-byte information memory segments. A segment is the minimum unit of erase granularity, but bytes within an erased segment can be written individually. The main and information memories would typically correspond with an application program and nonvolatile data, but there’s nothing in the architecture that demands such a split (i.e., program and/or data can be stored in either memory).

The flash memory offers guaranteed 10k (minimum) cycle write endurance, which is the hardest to meet at the cold extreme of the standard –40° to 85°C temperature range. However, in more temperate environments, the datasheet indicates that 100k cycles is typical. Worst-case data retention is 100 years. That’s a lot better than many chips’ 10-year specification, which is questionably short for long-life embedded apps.

Rather luxurious for an entry-level chip, there’s also on-chip flash memory programming voltage (i.e., VPP) generation, with the proviso that VCC must be kept between 2.7 to 3.6 V during program and erase, versus 1.8 to 3.6 V (’110x) or 2.2 to 3.6 V (’112x) for normal operation.

It’s impressive that the flash memory can be programmed in three ways. The first is via the JTAG port that is also used for debugging. The second option is in-system programming under control of your application software. Because the entire flash memory becomes inaccessible during program and erase, the programming routine must be loaded into RAM for execution. Fortunately, the needed code is trivial because all the low-level details are handled in hardware. The setup is hardened against self-lobotomy with access keys, protected against improper operation or unexpected hardware events, and even has an emergency exit bit, should things get out of hand.

Best of all, there is a bootstrap ROM monitor built in (see Figure 2). Normally, the TEST pin is used to switch four port pins between JTAG or I/O operation. However, tickling the TEST pin just right (two rising edges) at *RST causes the bootstrap ROM to take control. Communicating with a host via two port pins configured as a 9600-bps UART, the bootstrap ROM includes functions to erase, read, and write the flash memory, as well as accessing on-chip RAM and peripherals.

Figure 2—The top 60 KB is set aside for flash memory and the bottom 4 KB accommodate special function registers (SFRs), 8- and 16-bit memory-mapped peripherals, RAM, and 1-KB boot ROM for easy flash memory programming.

Rock and Clock

Fancy clock generators are the rage, which isn’t surprising considering their effect on power consumption. The ’F11x diagram just shows an oscillator system clock, but under the hood it’s as fancy as anything out there (see Figure 3).

Figure 3—The clock generator features on- and off-chip sources, extensive configuration options, and complete software control.

The chip takes advantage of selectable internal or external clock sources. The XIN and XOUT pins provide connections for a 32.768-kHz watch crystal or a high-speed (up to 8-MHz) crystal, resonator, or external clock. Other higher pin count members of the ’430 family (e.g., the ’F13x and ’F14x) even include a connection for an optional second external crystal.

On-chip there’s a digitally controlled RC oscillator (DCO) with eight software selectable rates between 100 kHz and 5 MHz, and also the option to set timing with an external resistor. As with all RC oscillators, there’s a fair amount of temperature and voltage drift, on the order of ±10% of the nominal setting.

To improve, TI added a modulation feature. In addition to the basic one-of-eight setting, a 5-bit MOD field sets a duty cycle at which the DCO switches between the desired and next higher DCO setting. Assuming an accurate timebase is available (e.g., watch crystal), software can periodically recalibrate by fine-tuning the DCO. MOD is a 5-bit field, yielding about 3% control (32 selections). Because the basic eight steps for the DCO represent about 10% each, that means overall tuning is only a fraction of 1% over the long term (32 cycles), with the under- standing that there will be clock-to-clock jitter (DCO step size).

Either the crystal or DCO oscillator (or both) can be individually enabled and disabled. After powerup, during which the DCO is the default clock source, software can switch to the external clock. In this instance, the DCO acts as a fail-safe clock source in case the external clock disappears.

In turn, the two source clocks, crystal and DCO, selectively drive three on-chip clocks, each via its own independent 1/2/4/8 programmable divider. MCLK is the master CPU clock, and peripheral modules can be independently programmed to use either SMCLK or ACLK. ACLK is sourced from the external crystal, and SMCLK can be sourced from either the crystal or the DCO.

A full quiver of five power modes derives from the various clock sourcing and routing options, ranging from Active, with all clocks operating, to Low-Power mode 4, in which everything stops and only the RAM, registers, and I/O port contents are retained.

It’s no surprise that low voltage and a leisurely clock rate make for miserly power consumption, but I was surprised by how low these parts go (see Figure 4). Even fully active with both the DCO (1 MHz) and crystal oscillator (32.768 kHz) running, you’re talking about 1 µW or so. Stepping through ever-lower power modes, that already miniscule demand is further cut by a factor of 10, and then by 100. Batteries will last a long time, which is nice for customers and the environment.

Figure 4—For price and power, the ’F11x seems more like a 4-bit than a 16-bit chip. Even fully active at 1 MHz (power scales linearly with frequency), power consumption is miserly and drops further in various power-saving modes.

Time Trip

Rounding out the ’F11x peripherals are the parallel I/O ports and 16-bit Timer_A.

The general-purpose I/O port setup is clean. Every bit has a place in seven registers—input, output, direction, interrupt, interrupt edge select, interrupt enable, and selection—as either general-purpose or on-chip peripheral I/O. As the list implies, any pin can be used as an interrupt source. I was surprised to see no I/O port characteristics (e.g., totem-pole versus open-drain) or pull-up options (we’re getting spoiled, aren’t we?).

By contrast, no feature is left out of the Timer_A, which offers an array of options starting with four choices for the clock (two external pins and the aforementioned ACLK and SMCLK on-chip clocks). The chosen source then feeds a 1/2/4/8 programmable divider to generate the timebase for three separate capture and compare channels with various pin and trigger options.

There’s also a 16-bit watchdog timer with eight selections for the timebase. Half of the selections are based on SMCLK, and half on ACLK. In a typical configuration (e.g., high-speed crystal or DCO on SMCLK or the watch crystal on ACLK), this allows a broad selection of timeouts, from microseconds to seconds. The watchdog comes up enabled at power-up, but can be used as an interval timer instead by setting a control bit that makes it generate a regular interrupt instead of a RESET.

Re-Animator

TI’s "Two Bytes Are Better Than One" advertisement may not have aged well, but maybe the message is more timely than ever. I must say, I felt more than a bit of TMS 9900 déjà vu as I waded through the ’F11x docs, so much so that I actually scrounged around for an old datasheet.

Yes, it’s all coming back. The ’9900 featured a scheme based on only three registers—the PC, a status register, and a work space pointer. The work space pointer pointed to a 16-word window within the memory that was accessible as registers, requiring only short 4-bit fields in the opcode. The only problem was that, because these registers were really off-chip memories, access was slow (extremely slow if you funnel the 16-bit accesses through an 8-bit off-chip bus like the ’99/4 designers did).

On the plus side, the architecture is clean. It’s a CISC, but it’s not plagued with the warts and restrictions like other chips made in that time. Notably, the architecture was pretty regular in terms of allowing an arbitrary mix of instructions, registers, and addressing modes. Arriving on the scene years before the 68K and other chips that touted the same advantages, the ’9900 was well ahead of its time.

The MSP430 CPU architecture isn’t a TMS 9900 in drag, but it does carry forward many of the same basic concepts. The most obvious change is the addition of a real register file. Otherwise, the philosophy of a simple instruction set with general-purpose registers and plenty of addressing modes remains unchanged.

In fact, with a mere 27 native instructions, the TI part is a CISC that is more reduced than most RISCs. For your programming convenience, a couple of dozen extra instructions are synthesized. But even the entire complement would have to be considered lean and mean by anyone’s standards.

Thanks to the addition of a real register file, coupled with its CISC roots, the ’430 supports your favorite programming style. Those of you who prefer a RISC approach can utilize the register file in a load-and-store fashion and other people can take advantage of the easy addressing to do everything in memory.

Get On Board

With their flash memory, low power, and competitive price, the TI parts are great. But, it’s going to take more to make a dent in the contested MCU market. In particular is the need to seed and support thousands of designers instead of just a few focus accounts, which can be problematic for companies that are used to dealing with only a few big customers.

Whether or not TI has the commitment and staying power remains to be seen, but it seems to be making all the right moves. Case in point: TI recently signed Digi-Key as a distributor, a must for anyone hoping to be a contender against major competitors like Motorola and Microchip. TI also offers low-cost, surprisingly useful EV kits.

I couldn’t resist fooling around with the $49 Flash Evaluation Tool (FET, see Photo 3). This little puppy takes full advantage of the ’F11x flash memory, low power, and on-chip debug logic.

Photo 3—People complained that you needed a TI minicomputer to develop programs for the ’99/4. Not so with the ’F11x controller; just a PC and $49 EV kit will do the trick.

I admit that I got off to a bit of a rocky start and was reminded why I never became a brain surgeon, as I fumbled with getting the tiny surface-mount chip properly seated in the "I’m-amazed-it-works" spring-loaded ZIF socket.

The good news is, with their low-power advantage, EV power is supplied by the host PC parallel port, so there are no wall warts. The bad news is that some notebook PCs’ parallel ports don’t cut it. The other good news is that TI states this in its read-me-first docs. More bad news, no one reads that stuff. Switching to a desktop PC got me on the air.

The board comes with a demo version of the IAR Embedded Workbench tool chain that includes the whole shebang—C compiler, ASM, debugger, simulator, IDE, and so forth (see Photo 4). There are demo restrictions such as a 1-KB C code limit, but the useful stuff (e.g., ASM, debug, and simulator) is functional. Support by IAR, one of the leading MCU tools suppliers, lends further credence to the TI campaign.

Photo 4—The EV kit includes a surprisingly functional demo version of IAR’s luxury liner Embedded Workbench tool chain, which also can be downloaded for free from TI’s web site.

Back to the Future

To say that a chip that traces back 25 years could be a hit today sounds funny. That’s progress? Maybe it is. There are plenty of other old-time MCUs out there to keep TI company.

Sometimes chips that were a good idea yesterday are still a good (maybe even better) idea today. I think the MSP430 family has a lot going for it.

Maybe what the world needs is a new MSP430-based ’99/4-plus. On second thought, for the chip’s sake, better let that sleeping skeleton lie.