Tweed99

Conversion is always a hot topic, but David’s not talking religion here. Instead, he wants to fill us in on the basics of A/D and D/A conversion, so that we’ll be ready to delve into the deeper issues in the coming months.

Signal processing in the digital world requires that analog signals be converted to discrete units in both a measurement dimension (voltage, current, temperature, etc.) and time.

The former is called quantization, and the latter is known as sampling. While these conversions can be analyzed independently by a mathematician, a real-world analog-to-digital converter deals with both simultaneously.

Similarly, when digital processing is complete, it’s often necessary to convert the signal back to a continuous-measurement, continuous-time domain. That’s the job of the digital-to-analog converter.

In this series, I discuss the fundamentals of A/D and D/A conversion. Part 1 covers the basics of reading and understanding specification sheets. Part 2 introduces the most important conversion technologies as well as their strengths and weaknesses, relative to the parameters I cover. In the final article, I delve into delta-sigma conversion and show you how to dither.

An ADC maps an analog measurement to a set of digital codes that can be conveniently manipulated. In the ideal case, this mapping is perfectly linear and can be drawn as a straight line on a graph. However, the fact that the analog domain is continuous and usually unbounded while the digital side has a finite set of codes creates two ways in which the graph deviates from the straight line.

First of all, the converter’s range has definite endpoints. All analog values outside this range simply map to the highest and lowest codes.

Also, each digital code represents a small range of analog values, creating a stepwise mapping from the analog to the digital domain, as Figure 1 shows.

Figure 1—In an ideal world, converters have transfer functions that approximate straight lines. ADCs translate ranges of input values to discrete codes, and DACs translate those codes to specific output values.

Similarly, a DAC maps digital codes into analog values. Given the finite set of digital codes, there must also be a finite set of discrete analog values the converter can generate. For an ideal converter, these points lie along a straight line.

Figure 1 shows the transfer functions for an ideal three-bit ADC and the corresponding three-bit DAC. The dashed line represents the ideal straight-line transfer function that each unit tries to approximate.

As you see, the ADC divides the analog domain into a series of ranges and assigns one digital code to each range. The range on each end is open-ended, while the six intermediate ranges are the same fixed size.

The eight ranges are defined by seven decision levels or input values that cause the converter to switch from one code to the next. In real applications, the end ranges are usually the same size as the intermediate ranges, and a single value is associated with each range that is the midpoint of the range. The size of each range is called the step size or quant (i.e., quantum or smallest perceivable change).

The corresponding three-bit DAC produces the single value associated with a range when given the digital code for that range. Together, the ADC and DAC form a system that has a stepwise linear transfer function.

The maximum difference (or error) between input and output occurs when the input value is very close to a decision level, and as you can see, the corresponding output value differs by half a quant one way or the other.

The values associated with the end ranges are known as full-scale values. In a unipolar converter, the lower end is usually zero and the upper end is a positive value (e.g.,
5 V). In a bipolar converter, the end values are plus and minus the same value (e.g., ą2.5 V). The converter’s range is the difference between the end values (here, 5 V).

The number of bits in the digital code determines how many codes there are by a simple relation:

This equation gives the number of input ranges for an ADC or the number of output values for a DAC. Since the input ranges are the same size, their size is given by:

Think of the quantized signal as the sum of the original signal and an error signal introduced by the quantizer, as shown in Figure 2. Horizontal dotted lines represent the decision levels.

This error signal varies in a complex way that depends on the input signal, so it is usually treated and analyzed as a noise source in the ADC.

However, to massage the noise signal you need to know how much noise is generated (amplitude) and what its spectral characteristics are (i.e., in audio systems, what does it sound like?).

If the peak amplitude of the error signal is limited to half a step size (in an ideal converter), how much power (loudness) does this represent? Assuming that the error signal is a sawtooth signal with a range equal to the step size, then its RMS value is:

or about 0.707 times its peak value. For an n-bit converter, the ratio of the sine-wave RMS voltage to the error signal RMS voltage is given by:

The converter’s range cancels out, so we are left with a simple expression that depends only on the number of bits:

This range is usually given in decibels (e.g., a logarithmic scale), which works out to:

This 3-bit converter has a signal-to-noise (S/N) power ratio of about 20 dB, but an ideal 16-bit converter should achieve 98 dB. Adding a bit of resolution increases the S/N ratio by about 6 dB.

Figure 2 shows how the characteristics of the error signal vary over the full cycle of the sine wave, which is often undesirable.

For example, in an audio converter, a low-frequency sine wave can noticeably modulate background noise, which is more annoying than a steady level. You can solve this problem by adding a randomizing signal (i.e., dithering it) before you quantize it.

The dither signal’s characteristics are chosen to mask the effects of quantization without becoming objectionable itself. I’ll discuss dither signals and their application more in Part 3.

A real-world converter isn’t going to have the perfect straight-line transfer characteristic of the ideal converter. Figure 3a shows some of the problems you may find in a transfer curve.

One way to get this converter working in an application would be to adjust the curve’s endpoints to the desired values, letting the intermediate points fall where they may (see Figure 3b). This way, it’s easy to calibrate by examining two points on the curve.

You can also find the best-fit straight line for the converter and calibrate that to the desired range, as shown in Figure 3c. This approach gives the lowest overall RMS error if the full range of the converter is used, but unfortunately, you need to examine a large number of points on the curve to find the best-fit line.

In either case, the deviations from the straight-line characteristic (known as nonlinearity) distort the analog signal’s digital representation. These distortions are the same as you’d find in a purely analog nonlinear system and are broadly classified as harmonic (waveform) distortions and intermodulation distortions (e.g., interactions among simultaneous signals).

Manufacturers have a number of ways to characterize their converters for distortion. One way, differential nonlinearity (DNL), is simply the variation of the step size for each digital code from the ideal theoretical value.

For an ADC, this is the difference between successive decision points, while for a DAC, it is the difference between successive output values. Figure 4a graphically depicts these results, placing the digital codes along the x-axis and the error associated with that code along the y-axis.

Integral nonlinearity (INL), which is just the transfer curve of the device, is another way to characterize distortion. An integral curve (see Figure 4b) can be generated by integrating over the differential curve. Vendors usually show one curve or the other, depending on which characteristic of their device they want to emphasize.

Which is more important? It depends on your application. If absolute accuracy is crucial (e.g., measuring a voltage or current in an industrial process), the integral nonlinearity is more important.

But in an audio application, integral nonlinearity represents an overall gain error that is, for all practical purposes, irrelevant. Differential nonlinearity gives a better idea of the audible distortions the converter produces.

Another way to characterize an ADC is to feed in a full-scale sine-wave signal and make a mathematical histogram of the number of times the converter produces each code, as you see in Figure 4c.

An ideal converter produces a specific curve (related to arc sine) under this test, and examining the way a histogram deviates from the ideal is a quick way to find potential problems, including missing codes that the converter never produces.

Some ADCs have larger than average nonlinearities when a more significant bit changes state (e.g., going from 00111111 to 01000000). In some cases, the decision level implied by 00111111 is actually slightly higher than that of 01000000.

A slowly rising signal generates a code sequence that jumps directly from 00111111 to 01000001, and the code 01000000 is said to be missing. While this miss doesn’t cause large problems in terms of the overall error or noise level, it can indicate an underlying problem, so, manufacturers like to boast "No missing codes."

You can characterize the overall linearity of a converter by specifying the spur-free dynamic range (SFDR), which is measured by applying one or two full-scale sine waves to the converter and doing a spectral analysis (e.g., FFT) of the output.

The SFDR is the ratio between the peaks representing the original signal(s) and the highest peak of any of the harmonic or intermodulation distortion products. This performance measurement is most important in the high-speed converters used in digital radios but can be important in other applications as well.

As mentioned, the codes in a DSP’s memory represent points or discrete values along the measurement and time axes. Quantization gets us the first, and sampling gets us the second.

Shannon and Nyquist showed that a continuous-time band-limited signal can be perfectly represented by a set of discrete samples as long as the sample rate is greater than twice the bandwidth of the signal.

In many systems, the frequency band of interest includes DC, so it is often stated that the sample rate must be greater than twice the highest frequency in the signal. However, you need to make the distinction since there are systems in which the bandwidth is considerably narrower than the frequencies present (e.g., the IF stage of a digital radio receiver).

If a system fails to meet the Nyquist criterion, then aliasing occurs, causing signals at frequencies that originated outside the Nyquist bandwidth to have the same effect as a phantom signal within the Nyquist bandwidth. Once this happens, it’s impossible to separate the undesired signal from the desired signal (but see Gerard Fonte’s article in this issue).

If the signal is not known to lie within the Nyquist bandwidth, it must be filtered in the continuous-time domain before sampling occurs. Let’s look at two basic approaches to this.

You can place analog filters ahead of the ADC that attenuate out-of-band signals at or near the quantization step size. But if signals just within the Nyquist bandwidth are important to the application, you need high-order filters with steep skirts. These filters tend to be complicated (high parts count) and difficult to adjust, and they introduce undesirable phase shifts.

The second approach minimizes these effects by oversampling (i.e., using a much higher sample rate initially). This technique raises the Nyquist frequency, enabling you to use a much simpler analog filter. Digital-filtering techniques that are easier to control and that have better phase characteristics can reduce the bandwidth before resampling the signal at the desired final sample rate.

Delta-sigma–based converters take this to the extreme by using a one-bit converter at a very high sample rate to achieve the performance of a multibit conventional converter. I’ll cover delta-sigma conversion in Part 3.

Just as there can be small errors in the exact placement of decision points in an ADC’s measurement domain or in the placement of output levels in a DAC, both kinds of converters can have small errors in the time the samples are taken or generated. This error is called timing jitter.

As Figure 5a shows, errors in the horizontal (time axis) placement of samples by a DAC produce errors in the resulting waveform that are similar to quantization noise. The magnitude of the error in the measurement domain is related to the size of the timing error by the slope of the signal. For a DC signal, timing jitter has no significance, but signals near the converter’s bandwidth limit have a serious effect.

In the worst case, a converter will slew over its entire range from one sample to the next, so a timing error producing a one-quant error equals the sample period divided by the number of steps. For CD-quality audio (i.e., 16 bits at 44,100 samples per second), this works out to 346 ps (10–12 s), which is very tiny indeed.

A more typical example is a full-scale 1-kHz sine wave, which has a maximum slew rate of 4669 steps per sample. A 4.85-ns timing error produces a one-quant error here.

However, it’s rare for even a relatively inexpensive crystal oscillator to have 0.5 ns of jitter. It’s pretty safe to ignore most of the breathless hype you read about the horrible jitter problems of CD players.

Figure 5b shows how timing errors that affect when an ADC accepts its samples have the same effect when the samples are played back through a perfectly timed DAC.

Except for flash converters, which do their work instantly, most ADC technologies need a finite amount of time to complete a conversion. Many assume the signal won’t change significantly (more than the step size) over that period.

However, some systems can’t make that guarantee inherently. A sample-hold or a track-hold circuit is then placed in front of the converter that samples the signal in analog form and holds it during the conversion.

Figure 6a shows this kind of circuit. The input signal charges a low-leakage capacitor, whose voltage tracks the signal as long as the switch is closed. When conversion begins, the switch opens and the capacitor holds the level of the input signal for that moment. A buffer amplifier with an high input impedance keeps the voltage from changing until the switch closes again.

• how long it takes for the output to match the input once the switch closes again

• how long the circuit can hold the desired value to the needed degree of accuracy (droop rate)

Sometimes the signal controlling the switch feeds through to the circuit output, making the offset with the switch closed different than with the switch open. It’s impossible to completely eliminate these errors, but you minimize them as much as possible relative to the converter’s resolution.

As Figure 6c shows, track-hold circuits also have applications in conjunction with DACs. Sometimes the output of a particular DAC has glitches at the moment a new sample comes along, rather than moving smoothly to the new value.

These glitches tend to be short relative to the sample period, and sometimes you can control them by simple low-pass filtering at the output of the DAC—the same filter that eliminates the images of the output spectrum.

If the glitch energy (amplitude multiplied by duration) is high, the heavy filtering required would cause undesirable effects to the signal, so a track-hold circuit is used to disconnect the DAC from the output for the duration of the glitch.

The mathematics of sampling theory assumes that the samples have infinitesimal width. However, because an impulse function has a flat frequency response (see Figure 7a), a train of such impulses has a spectrum that is a discrete version of a single pulse as illustrated in in Figure 7b.

As Figure 7c shows, a rectangular pulse has a sin(x)/x spectrum. As the pulse narrows, the spectrum widens. In the limit, the pulse becomes the impulse function and the spectrum is infinitely wide or flat. Figure 7d presents a train of rectangular pulses with a discrete version of the same spectrum.

What does this have to do with a DAC? As a designer, your concern is what the converter does in the time between the instants defined by the samples. The math assumes the function is zero between those instants, but real-world converters do some kind of interpolation.

First-order interpolation draws a straight line between one sample and the next. Second-order interpolation use a quadratic function, in which higher orders of interpolation use higher orders of polynomial functions.

In fact, most converters hold a value until the next sample comes along. This technique is called zero-order interpolation, zero-order hold, or sin(x)/x correction.

Mathematically, you can treat the DAC output as a series of rectangular pulses wide enough to completely fill the interval between the samples, as indicated in Figure 7e. Because DT1 equals DT2, the nulls of the sin(x)/x curve fall exactly on the harmonics of the sampling frequency, causing them to disappear.

However, the signal represented by the samples shows up in the frequency spectrum as sidebands around those harmonics, and they are attenuated by the sin(x)/x curve as well. To recover the original flat spectrum, a filter with a response opposite that of the sin(x)/x curve must be inserted into the path.

Now that I’ve reviewed many of the fundamental issues of A/D and D/A converters, you’re well equipped to discuss specific converter technologies next month.

David Tweed has been developing hardware and real-time software for microprocessors for more than 22 years, starting with the 8008 in 1976. His system design experience includes computer design from supercomputers to workstations, microcomputers, DSPs, and digital telecommunications systems. David currently works at Aris Technologies developing digital audio watermarking. You may reach him at dtweed@acm.org.