The SX MCU from Scenix is fast, runs on almost anything, gets good mileage, and you can park it anywhere. And, Parallaxs SX-Key makes for some easy riding. Will we be seeing biker bars in Silicon Valley?
Like other places, Silicon Valley goes through booms and busts. The only difference is that single-digit growth is considered a bust, while startups routinely post triple- or even quadruple-digit gains.
The boom of the last few years, fueled by I-way frenzy and bloatware-driven PC upgrades, has been one of the strongest ever (even though its fading a bit in the stretch). Its a veritable gold (err silicon?) rush.
One of the consequences is traffic with a capital "T". Ever fly into San Jose at 5:00 p.m., rent a car, and try to go somewhere?anywhere? I dont commute, but I get out enough to see just how ugly the jam-up is.
In my opinion, the ideal vehicle for our dart-and-weave stoplight-to-stoplight jousting is a motorcycle. Now, a bike isnt suitable for everythingcertainly not big jobs like hauling the brood around or moving furniture.
I also understand the objections from those of you who live in colder climes. And, theres the danger factor, though two-wheel advocates argue that slow mummification behind the wheel isnt a real pleasant way to go either.
I rode a bike years ago when I was a commuter for the same reasons I give today. Theyre relatively inexpensive to own and operate, theyre allowed to use the carpool express lanes, and you can always find a parking space.
But, the most compelling advantage is speed! At the time, my 750 was faster off the line than practically any car on the road.
The inspiration for this thread is the appearance of the SX MCU from startup Scenix Semiconductor. Like a bike, its small, relatively inexpensive (under $4 in small quantities), and most important, fast. Im talking close to 50 MIPS, which is a good 1050 times faster than typical 8-bit MCUs.
Its no problem finding parking for the SX, which is offered in a variety of small packages from 18 to 28 pins, including DIP, SOIC, and SSOP. It isnt finicky about fuel either, running on anything between 3.3 and 6.25 V. It gets good mileage, consuming about 1 mA/MHz at full throttle and mere microamps when idling.
Take a close look at the motor (see Figure 1). Those of you familiar with Microchip PICs will notice a striking similarity. Indeed, the SX goes out of its way to offer PIC16C5x socket compatibility.
The novel in-system programming scheme (using the OSC pins) for the onboard 2K ´ 12 program flash is supplemented with a parallel programming mode similar to the PICs, with a slightly different algorithm.
Its possible to configure an SX as a PIC clone, but it probably doesnt make much sense. Alhough its not expensive, theres no way an SX is going to compete price-wise with the much higher volume PIC.
In fact, after considering the plethora of good 8-bit micros (including flash-based) on the market, two features stand out as compelling advantages for the SXperformance and innovative, low-cost, easy-to-use development tools.
The secret to SX performance is simple, relying as it does on the traditional technique of pipelining. The four-stage pipe in Figure 2 is a classic, similar to those found in earlier (but typically larger, like 32-bit) machines.
Figure 2SX performance is obtained via pipelining using a time honored fetch-decode-execute-writeback design. Since a pipeline can only run as fast as its slowest stage, great attention was paid to the flash-memory design to achieve the 10-ns access time required by the 50-MHz clock rate. |
There is one, and only one, reason to use a pipeline and thats to boost the clock rate, which ultimately is limited by memory access time.
In compatibility mode, the SX reverts to four clocks per instruction (eight for JMPs and CALLs), same as a PIC. Flip the turbo switch, and the pipeline kicks in.
Once filled, the pipe delivers close to one instruction per clock. However, as with all pipelined machines, there are some caveats to be aware of.
The JMP and CALL penalty is relatively worse due to the need to refill the pipe. Where such instructions require two cycles (eight clocks) in compatible mode, they need three cycles (three clocks) in turbo mode, derating the advantage to 2.66´ (8 divided by 3) for those instructions versus 4´ for most others.
Another example is IREAD, one of the ten new instructions added by Scenix (see Table 1). IREAD enables a program to read the instruction memory, something thats nontrivial in a Harvard design (separate program and data memory).
Command |
Description |
|---|---|
| PAGE n | Switch to new instruction page |
| BANK n | Switch to new register bank |
| RET | Return without affecting W |
| RETP | Return across page boundary |
| RETI | Return from interrupt and restore state |
| RETIW | Return from interrupt and reload timer |
| IREAD | Read instruction memory |
| MOV !M,W | Write I/O mode bits |
| MOV W,!M | Read I/O mode bits |
| MOV !rx,#imm | Write immediate to port control register |
| Table 1To ease programming and accomodate new features, Scenix adds 10 new instructions for a still RISCy grand total of 43. | |
Given the complication involved, IREAD requires the same number of clocks (four) in both compatibility and turbo mode. But, its faster than previous data-lookup schemes and can access the entire code space.
Pipelined machines are also subject to various hazards that must be obviated by hardware, software, or both (e.g., the problem of trying to read data at the same time its being written).
Consider a sequence of instructions involving a back-to-back write followed by a read of the same data. Instruction n is writing data (write stage) even as instruction n + 1 (execute stage) wants to read it.
With on-chip RAM, the SX includes forwarding logic that handles such an obstacle transparently in hardware. Thus, one instruction can write to RAM and the next one can safely read from the same location. However, for I/O ports, there are precautions concerning successive operations.
For pins configured as outputs, the SX reads the actual pin level, not the output latch. I think the SX approach is superior because it enables the detection of external problems such as a shorted or excessively loaded pin.
Its easy to confirm that the output-pin level is or isnt what its supposed to be. By contrast, reading the output latch, rather than the pin, leaves you blind to outside interference.
As a consequence, a write to a port may not propagate through to the pin in time to be recognized by an immediate read. Depending on the clock rate and pin loading, a non-port instruction should be inserted to split up a back-to-back port write and read. Similarly, the possible difference between output latch and pin level calls for care when using read, modify, and write instructions like SETB and CLRB.
The I/O pins themselves (4-bit Port A, 8-bit Port B, and, for 28-pin devices, 8-bit Port C) are versatile. Each pin is individually programmable as input or output, with or without an internal pull-up resistor. All inputs are selectable as TTL or CMOS levels, and Port B and Port C inputs can be individually defined as Schmitt triggered.
Outputs can sink and source 30 mA (subject to overall device power limit), with those on Port A featuring symmetrical drive (i.e., centered about VDD/2 under any load). This feature is useful for driving speakers and other pseudoanalog functions such as using a PWM to implement a DAC.
As inputs, pins of Port B can be individually enabled to act as wakeups (with programmable edge selection) from low-power sleep mode. Or, three pins of Port B can be configured as an analog comparator. Two inputs (RB1 and RB2) are compared with the result (greater than or less than) reflected on output RB3.
Besides general-purpose I/O, the SX includes an 8-bit timer/counter (RTCC) and watchdog timer, either of which (but not both at the same time) can be mated with an 8-bit prescaler.
The inertia of a full-size four-wheeler isnt a good match with stop-and-go traffic. The only winners are OPEC and brake shops.
The same goes for chips and interrupts. The grander the CPU, the more energy and time wasted finishing off instructions in progress, saving a bunch of registers, and making the turn toward the handler. Here, bikesand the SXhave a big advantage. Less iron to stop and get going again means a quick and efficient response.
Interrupt sources include the RTCC and pins of Port B configured for wakeup (if the SX isnt sleeping, a wakeup functions as an interrupt).
Most CPUs require the instruction in progress to complete before anything else happens, but not the SX. To cut response time to the bone, the SX aborts instructions in the pipe. It also includes a set of shadow registers that automatically capture the critical state.
The end result is a blazing interrupt response: only three clocks for an RTCC interrupt and five clocks for external interrupts. Thats 60/100 ns (RTCC/external) at 50 MHz. Thanks to the shadow registers, returns from an interrupt are equally speedy at three clocks.
Another nice thing about bikes is theyre easy to work on, requiring only a small set of basic tools. Its the same with the SX, thanks to the SX-Key from Parallax.
This nifty gadget, shown in Photo 1, exploits the fact that the SX has programming and debug logic onboard, accessed via the OSC pins. In-system programming and debugging for any SX-based design is a simple matter of incorporating a four-pin header (OSC1, OSC2, power, ground). For programming, the OSC pins act as a serial download channel, while during debug, the SX-Key has explicit clock control.
Photo 1Like the SX, the SX-Key development tool from Parallax packs a lot of punch into a small package. |
Three packages are offered for your riding pleasure. The Skeleton Key ($249) is just the SX-Key and software tools. The Master Key 18 ($319) adds a proto-board with buttons and LEDs (see Photo 2a). The Master Key 28 ($349), shown in Photo 2b, comes with a fully loaded demo board including buttons, LEDs, RS-232, an external EEPROM, and a speaker.
a)
Photo 2aIncluded in the Master Key packages, Parallax offers a QuickProto board (with Master Key 18 package, or $69 separately) and bDemoBoard (with Master Key 28, or $99 separately). |
On the roads these days, theres a remarkable proliferation of SUVs. Folks seem to think they need a cross between a Humvee and a Mack truck to get across town. Its kind of equivalent to the bloatware phenomenon that curses our PCs.
Not so with the SX-Key software (Win 95 and up), which is blessedly simple, boiling down to three screens: one for editing your ASM program, one for configuring the SX, and the debug screens in Photo 3.
Photo 3aThe Parallax SX development software handles configuration and programming of the chip. bIt also handles debug of ASM programs. Notice the Parallax-defined mnemonics and multiword macro instructions. |
The set-up screen offers a good opportunity to top off the SX feature list. You can see the variety of clock options (crystal, resonator, RC, and internal 4 MHz with an eight-stage divider), configurable brown-out reset, extended stack (eight levels versus the usual two), tweaked operation of the carry bit, optional input synchronizers (metastability insurance at high clock rates), and so on.
The assembler uses the Parallax mnemonics popularized on their earlier generation of PIC tools (there is a utility available to convert existing PIC code to the SX/Parallax mnemonics). Also, Parallax has defined a number of convenient macro-instructions that consolidate common sequences of single-word instructions into easier-to-use formats.
For those of you so inclined, theres a C compiler from Byte Craft. Data-type support is impressive with 8-, 16-, 24- and 32-bit INTs, and even IEEE-754 floating point, though I suspect its easy to bite off more than a 2K-word SX can chew.
Its not cheap ($795 DOS, $1495 Win 95/98/NT), but Ive always found that C compilers embody that old axiom "you get what you pay for."
One open issue involves integration of the Byte Craft and Parallax tools. At the time of this writing, they arent really connected. However, both companies are planning a cozier relationship.
The conventionally wise will proclaim the concept of a high-performance 8-bit MCU as an oxymoron. Its true that the majority of apps are, and will continue to be, well served by the few MIPS most MCUs can muster. Yep, dont expect to see your average commuters crowding the Harley dealer, either.
Fact is, I think Scenix might be onto something. With performance to burn, the SX handles many functions in software that might otherwise call for extra silicon.
The concept of replacing hardware with software (Scenix refers to virtual peripherals) isnt new. In fact, some of the earliest micros were used to just such an end. Witness the 8048 called into duty as a keyboard encoder in the original PC.
The difference is that the SX performance headroom boosts the specs of the usual peripheral functions like serial I/O, software timers, and waveform generation. More speed, more channels, or both.
For instance, consider the well-known hack of building a UART in software. Transmitting is easy since timing is under the control of the programmer. But, reception is another story. Few apps can afford to dedicate all bandwidth to polling the serial line, so interrupts are required.
Thus, the achievable data rate is directly related to interrupt latency, which should be less than half the bit time. For instance, most 8-bit MCUs can handle 9600 bps, which enables a leisurely 50+ ms from the leading edge of the start bit (that generates the interrupt) to the first sample.
But, higher data rates are a dicey proposition. For instance, 115 kbps needs an interrupt response of less than 5 ms. Speed not only becomes an issue, but jitter (i.e., nondeterminism) is a factor as well. Consider the 8051, which can only guarantee response somewhere between 36 and 108 clocks, or 39 ms at a 12-MHz clock rate.
To be fair, much of the variance is because the 51, like most MCUs, requires completion of the instruction in progress, including the relatively slow (48 clock) MUL and DIV, which the SX doesnt have. Banning MUL and DIV would cut 24 clocks (2 ms at 12 MHz), making a worst-case response of 7 msstill not fast enough.
Its worse than it sounds because Im just talking about the raw interrupt response. More time is needed to save critical state (PSW and any other registers), not to mention the instructions required to sample, compare, flag an error (false start bit), and so on.
By contrast, running at 50 MHz with five-clock external interrupt response (i.e., 100 ns) makes 115 kbps seem like a leisurely Sunday ride. I suspect you could hit 1 Mbps before going to full throttle. When it comes to interrupts, the SX blows the pins off regular MCUs.
The extra bandwidth doesnt mean doing old stuff faster. It lets the SX accept the challenge of significantly snootier I/O (e.g., music and voice synthesis and software video generation).
Scenix recently announced the availability of a Bell 202/CCITT V.22-compatible 1200-/2400-bps modem implemented in software, including not only the raw signal processing (FSK/DPSK) but also all the accessories (DTMF generation and detection, call progress detection, and caller ID).
Yeah, you can stick to your regular 8-/16-bit econo-chip for basic transportation, but remember that the fast lane is for passing. When that dot in the mirror turns into an SX hugging your tail, youve got two choices: move over or get run over.
Tom Cantrell has been working on chip, board, and systems design and marketing in Silicon Valley for more than ten years. You may reach him by E-mail at tom.cantrell@circuitcellar.com, by telephone at (510) 657-0264, or by fax at (510) 657-5441.SX-Key
Parallax, Inc.
(916) 624-8333
Fax: (916) 624-8003
www.parallaxinc.com
C compiler
Byte Craft Ltd.
(519) 888-6911
Fax: (519) 746-6751
www.bytecraft.com