November
1998, Issue 100
Smart
Rocket
SX
APPEAL
The
conventionally wise will proclaim the concept of a high-performance
8-bit MCU as an oxymoron. It’s true that the majority
of apps are, and will continue to be, well served by
the few MIPS most MCUs can muster. Yep, don’t expect
to see your average commuters crowding the Harley dealer,
either.
Fact
is, I think Scenix might be onto something. With performance
to burn, the SX handles many functions in software that
might otherwise call for extra silicon.
The
concept of replacing hardware with software (Scenix
refers to virtual peripherals) isn’t new. In fact, some
of the earliest micros were used to just such an end.
Witness the 8048 called into duty as a keyboard encoder
in the original PC.
The
difference is that the SX performance headroom boosts
the specs of the usual peripheral functions like serial
I/O, software timers, and waveform generation. More
speed, more channels, or both.
For
instance, consider the well-known hack of building a
UART in software. Transmitting is easy since timing
is under the control of the programmer. But, reception
is another story. Few apps can afford to dedicate all
bandwidth to polling the serial line, so interrupts
are required.
Thus,
the achievable data rate is directly related to interrupt
latency, which should be less than half the bit time.
For instance, most 8-bit MCUs can handle 9600 bps, which
enables a leisurely 50+ ms from the leading edge of
the start bit (that generates the interrupt) to the
first sample.
But,
higher data rates are a dicey proposition. For instance,
115 kbps needs an interrupt response of less than 5
ms. Speed not only becomes an issue, but jitter (i.e.,
nondeterminism) is a factor as well. Consider the 8051,
which can only guarantee response somewhere between
36 and 108 clocks, or 3–9 ms at a 12-MHz clock rate.
To
be fair, much of the variance is because the ’51, like
most MCUs, requires completion of the instruction in
progress, including the relatively slow (48 clock) MUL
and DIV, which the SX doesn’t have. Banning MUL and
DIV would cut 24 clocks (2 ms at 12 MHz), making a worst-case
response of 7 ms—still not fast enough.
It’s
worse than it sounds because I’m just talking about
the raw interrupt response. More time is needed to save
critical state (PSW and any other registers), not to
mention the instructions required to sample, compare,
flag an error (false start bit), and so on.
By
contrast, running at 50 MHz with five-clock external
interrupt response (i.e., 100 ns) makes 115 kbps seem
like a leisurely Sunday ride. I suspect you could hit
1 Mbps before going to full throttle. When it comes
to interrupts, the SX blows the pins off regular MCUs.
The
extra bandwidth doesn’t mean doing old stuff faster.
It lets the SX accept the challenge of significantly
snootier I/O (e.g., music and voice synthesis and software
video generation).
Scenix
recently announced the availability of a Bell 202/CCITT
V.22-compatible 1200-/2400-bps modem implemented in
software, including not only the raw signal processing
(FSK/DPSK) but also all the accessories (DTMF generation
and detection, call progress detection, and caller ID).
Yeah,
you can stick to your regular 8-/16-bit econo-chip for
basic transportation, but remember that the fast lane
is for passing. When that dot in the mirror turns into
an SX hugging your tail, you’ve got two choices: move
over or get run over.
