November 1998, Issue 100

Smart Rocket

THROTTLE RESPONSE

The inertia of a full-size four-wheeler isn’t a good match with stop-and-go traffic. The only winners are OPEC and brake shops.

The same goes for chips and interrupts. The grander the CPU, the more energy and time wasted finishing off instructions in progress, saving a bunch of registers, and making the turn toward the handler. Here, bikes—and the SX—have a big advantage. Less iron to stop and get going again means a quick and efficient response.

Interrupt sources include the RTCC and pins of Port B configured for wakeup (if the SX isn’t sleeping, a wakeup functions as an interrupt).

Most CPUs require the instruction in progress to complete before anything else happens, but not the SX. To cut response time to the bone, the SX aborts instructions in the pipe. It also includes a set of shadow registers that automatically capture the critical state.

The end result is a blazing interrupt response: only three clocks for an RTCC interrupt and five clocks for external interrupts. That’s 60/100 ns (RTCC/external) at 50 MHz. Thanks to the shadow registers, returns from an interrupt are equally speedy at three clocks.