The
SSP module begins to send the bitstream immediately
after the first word is loaded into the FIFO.
Any random deviations (caused by multitasking)
of delay between the PWM interrupt request and
the writing into the SSP data register will cause
the jitter of horizontal lines.
To
prevent this problem, I use a pair of PWM interrupts
(instead of a single one) with the minimum possible
duration between them. After the first request,
all of the interrupts (except the PWM) are disabled
and the CPU is forced into Idle mode. Next, the
second interrupt from the PWM module resumes the
CPU with a predictable delay.
