Start • Simple Video Signal • Video with the LPC2138 • Video Algorithm • Tricks Used • Vertical Sync & Resolution • Video for other Apps • Oscilloscope • Implementation • Construction & Results • Generate Video • Sources and PDF

VIDEO ALGORITHM

The algorithm for generating a single TV line is simple. Every 64 µs for PAL (or 63.536 µs for NTSC), the PWM block produces a horizontal sync pulse and simultaneously generates an interrupt that initiates the sequence of SSP cycles for a single TV line.

Because the SSP module has only 128 bits of its own memory (eight 16-bit FIFO frames), it can’t contain all the data for a 512-pixel line. To create a continuous bitstream, a new chunk of data should be loaded into the SSP as soon as there’s room for it. For this purpose, I use the “half empty” interrupt. This means that every time the FIFO becomes half empty, it requires the new portion of data. I assigned both the PWM and SSP interrupt requests to the FIQ category because the FIQ has a high priority and the fastest possible latency (see Figure 3). The disadvantage is that the FIQ handler should first identify which source is requesting the interrupt. Although it isn’t a recommended method, this is a unique way to create a glitch-free video when the other tasks use the vectored interrupt controller. (In this case, they must use only the IRQ category of interrupts!)

As you can see in Figure 3, when the FIQ is identified as coming from the PWM module, the SSP module’s FIFO is completely filled and its interrupt is enabled. This means that the SSP starts to output the content bit by bit and frame by frame. When the FIQ is classified as coming from the SSP module, this means that the FIFO is half empty and the next data chunk should be loaded into the FIFO again. When all of the chunks for a single TV line have been processed, the SSP interrupt is disabled for the next interrupt from the PWM.

The SSP module has a specific prescaler so a required bit rate can be chosen from fixed values: b = 60 MHz/2n (i.e., b = 30, 15, 10, 7.5 Mbps, etc., where 60 MHz is the nominal clock of LPC2138). These values correspond to the horizontal resolutions of 1,536, 768, 512, 320 pixels, and so on. (The horizontal blanking interval is taken into account.) I achieved all of the resolutions in practice. Note that the maximum resolutions of 1,536 and 768 aren’t applicable for color TVs because the color cathode ray tubes have discrete three-color dots on the surface of the screen.

To obtain the required TV frame structure, a TV line counter is provided in the software. The counter is incremented every time the PWM interrupt occurs. The current value of this counter is compared with a specific number to trigger a specific operation at a particular instant. Specific numbers define a vertical position, the height of the picture, and the duration of the vertical sync.