Table 1—Here are the timing values for the circuit illustrated in Figure 1.
|
Timing parameter
|
Minimum value
|
Maximum value
|
| Nominal CLK frequency | 25 MHz | 25 MHz |
| CLK to Q delay (both flip-flops) | 2 ns | 5 ns |
| Clock delay | 1 ns | 3 ns |
| Propagation delay through logic gates 1 | 3 ns | 15 ns |
| Propagation delay through logic gates 2 | 5 ns | 12 ns |
| D input setup time to CLK (both flip-flops) | 10 ns | |
| D input hold time after CLK (both flip-flops) | 6 ns |