Issue 160 November 2003
Timing (Analysis) is Everything
A How-To Guide for Timing Analysis

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Start • How is it Done? • Timing Diagrammer Pro • Automatic CAD Tools • Sources and PDF

As a hardware designer and manager, I’ve noticed that many electrical engineering students are often missing something when they begin their first full-time jobs. They’ve been taught how to design great circuits, some of them quite complex, but they haven’t been taught the importance of timing.

What does timing analysis mean? Why is timing analysis important? How is it done? In this article, I answer these questions. In addition, I present you with a real design problem that was solved with timing analysis. So, here we go! 

WHY TIMING ANALYSIS?

There are a couple of reasons for performing timing analysis. First and foremost, it can be used to verify that a circuit will meet all of its timing requirements. Timing analysis can also help with component selection. An example is when you are trying to determine what memory device speed you should use with a microprocessor. Using a memory device that is too slow may not work in the circuit (or would degrade performance by introducing wait states), and using one that is too fast will likely cost more than it needs to. 

A WORKING DEFINITION

Timing analysis is the methodical analysis of a digital circuit to determine if the timing constraints imposed by components or interfaces are met. Typically, this means that you are trying to prove that all set-up, hold, and pulse-width times are being met.

A minimum or maximum digital simulation is not actually the worst-case analysis. That is what a number of entry-level engineers believe. The worst-case analysis takes into account minimum delays through some paths and maximum delays through other paths. For instance, the worst-case set-up timing with respect to flip-flop B in Figure 1 would be the minimum delay to the clock input combined with the maximum delay to the data input of flip-flop B.

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Figure 1—The simplified digital circuit contains delays in the data and the clock paths. The timing values are shown in Table 1.

Let’s assume the timing values in Table 1 are for the circuit elements in Figure 1. Do you think that there is a problem with these values? Take a look at this circuit in a waveform view in Photo 1. Notice that the bottom of the photo shows the parameters used in determining the set-up and hold timing. Red indicates that a condition has not been met. If the set-up time is read and has a margin of –1, the set-up time has not been met and is off by 1 ns. The hold time indicates that there is 1-ns margin.

Table 1—Here are the timing values for the circuit illustrated in Figure 1.

In Photo 1, the gray areas of the waveforms indicate the uncertainty of when the edge occurs. Notice that the output of logic gate 2 has the largest uncertainty, because the uncertainty is cumulative as you go through a delay chain. So, the delay at the output of logic gate 2 is equal to the delay from CLK A to Q of flip-flop A as well as the delays through logic gates 1 and 2. Note that the waveform also uses color highlighting to indicate that constraints are not being met.

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Photo 1—I used Timing Diagrammer Pro for the timing analysis of the simplified digital circuit. Note that the gray areas on the waveform denote regions of uncertainty. The red areas show a timing violation.

As you can see in Photo 1, there is a D input set-up time problem to flip-flop B. Sometimes, when discussing timing issues, I hear designers say that timing doesn’t really matter because the processor has a memory controller with variable timing. This may be true, but it usually means that the processor allows for a programmable number of wait states. If you add another wait state (i.e., one more clock cycle before clocking in the data), then the problem in Photo 1 will go away. But what if you don’t want the performance hit of adding a wait state, or what if the processor doesn’t allow wait states? You would have to solve the timing problem.

Another case involves hold problems. Adding wait states often cannot solve this, because the timing chain for the D input is tied to the current clock edge not to the delays from the previous clock edge. In such a case, you need to make some changes to the design to make the timing work.

Okay, so you agree that there is a problem. So what? What will happen if you don’t fix it? There are three possibilities for set-up and hold times (see Figure 2).

As you can see in Figure 2a, the signal of interest can meet the timing with proper set-up and hold times. The next possibility is that the signal may miss it completely and get caught on the next clock edge (see Figure 2b). (Note that this can be a problem if you don’t want the performance penalty.)

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Figure 2a—Data arrives before the set-up time requirement. Data is clocked into the flip-flop on the rising edge of CLK. b—Data arrives after the hold time, which results in the data being clocked into the flip-flop on the next rising edge of CLK. c—Data arrives within the set-up and hold window, which results in an indeterminate output from the flip-flop.

The last possibility is that the input signal changes inside of the set-up and hold window (see Figure 2c). What happens in this case? The output of the flip-flop can become metastable, which means that the output can oscillate from zero to one or from one to zero a few times (or many times) before it stabilizes to a zero or one. The resulting state is random. (For more information on metastability, refer to H. Johnson and M. Graham’s book, High-Speed Digital Design: A Handbook of Black Magic). Obviously, this is not a good situation, because the output of the flip-flop may be wrong, and it may take longer than the normal propagation delay to get to the wrong value.

Knowing that you have a problem is the first step. So, how can you fix it? There are many ways to solve timing problems. In this simplified circuit, you are off by 1 ns. You can change either logic gates 1 or 2 so that they are faster parts. Another option is to select a flip-flop that has a smaller set-up and hold window. Timing analysis doesn’t fix the problem; it just tells you that there is a problem. Remember, when you make a change to your circuit, rerun the timing analysis to make sure that the problem is fixed and that another one hasn’t been created. Hopefully, I have convinced you that timing analysis is important. Now I’ll show you how to do it.