November
2000 , Issue 124
A
PIC17C44-Based Computer
THE
LATCHES
Device selection is accomplished by executing a TABLRD
or TABLWR instruction (see Table 1). RA<15:13>
are decoded to pull one of the CS lines low for 1 Tcy.
\
| 6000–7FFF |
CS3 |
Available |
| 8000–9FFF |
CS4 |
Available |
| A000–BFFF |
CS5 |
LCD (lines 1 and 2 of
4 × 40 LCD) |
| C000–DFFF |
CS6 |
Lines 3 and 4 of 4 × 40
LCD |
| E000–FFFF |
CS7 |
Keypad or piezo buzzer |
| Table 1—Here
are the device selection address range assignments. |
There
are three latches for CS5, CS6, and CS7, and one for
WR. Selecting CS5 or CS6 clears the CS7 latch. To clear
the CS5 and CS6 latches, select CS7. To clear the CS5
and CS6 latches without setting the CS7 latch, hold
RA3 low.
The
WR latch is set when any TABLWR instruction is executed.
The CS7 latch can be cleared by pulling RA3 low (level
activated). The WR latch can be cleared by pulsing RA3
low (edge triggered). In addition, RA3 is also used
as the register selection line for the LCD.
CS5
or CS6, which are latched in U2, select the LCD. Only
one can be selected at any given time and absolutely
must be cleared before the other can be set. U2B selects
E0 and U2A selects E1. WR is latched in U3A. RS is the
state of the RA3 pin.
When
reading, the LCD drives the data on Port B. And when
writing, the data must be on Port B. U1 (PIC12C50 8A)
polls for either selection. When either goes high, it
enables the LCD. When writing, U1 pulses E0 or E1 high
according to the selection latch outputs, then waits
for both latch outputs to go low before it resumes polling
for either high. When reading, it sets and holds E0
or E1 high until both latch outputs are low, then resumes
polling for either high.
The
PIC- 17C44 should be programmed to delay long enough
to allow the PIC- 12C508A to execute the instruction
sequence required for the LCD operation before changing
the RW latch or the data bus.
The
keypad decoder (U4) is selected by CS7, which is latched
in U3B. U4 drives the data on Port B. After reading
the data, U3B must be cleared by pulsing RA3 low so
that the data output lines of U4 return to hi-Z. When
CS7 is selected by a TABLRWR instruction, an open-collector
transistor activates the piezo buzzer. Before executing
either a TABLRD or TABLWR instruction, RA3 must be set
high and RB<7:0> must be hi-Z. Pulse RA3 low to
deselect CS7. When a key is pressed on the keypad, the
DA output of U4 goes high, setting RA0 high. You can
program this to invoke an interrupt.
