October 2005, Issue 183

The Silicon Wallet
CY8C27443-Based Data Manager

PSoC INSIDE OUT

I conceived this design as a building block suitable for reuse in many different devices. Therefore, efficient internal placement was one of my objectives. Actually, the placement takes only half of the analog and digital blocks available in a CY8C27443. Using as few I/O pins as possible is important as well, and the acquisition system requires only one extra pin other than the sensor input. The layout fills one digital row and one analog bi-column, making no restrictions on the use of the free blocks. The placement diagram is available on the Circuit Cellar FTP site.

A PSoC Designer’s PGA module placed in ACB01 implements the sensor amplifier illustrated in the block diagram. It amplifies 16 times the signal coming from PORT_0_0. Its reference input comes from ACB0, another PGA that implements the unity-gain offset control buffer. The offset voltage is generated by a DAC_6 placed in the switched-capacitor block ASD11. It’s necessary to use the sample and hold on to the output to get a continuous signal from the DAC. The I/O pin PORT_0_5 is used to bridge the DAC’s continuous output to the PGA input.

The low-pass filter is an LPF2 configured as a unity-gain, two-pole Butterworth. The filter’s placed vertically in ASC10 and ASD20. Its frequency cut-off is 670 Hz, and it’s internally connected to the sensor amplifier’s PGA.

The last analog block is the A/D converter that digitizes the signal coming from the filter, implemented as a delta-sigma converter by DELSIG8 in ASC21. This kind of converter requires only one timer module placed in DBB01.

As for the clocks, both the ADC and DAC take the clock from VC1 = SysClk/16, while the filter uses VC2 = SysClk/256. The CPU runs at SysClk/8 (more than adequate for this application) with nominal power set to 5 V.

The digital blocks create fewer restrictions during placement; you can lay them out in many ways. The proposed pattern has the advantage of being contained in the same digital row. Whatever the placement, remember to select the same clock for the DELSIG8 TMR and its analog counterpart. The design requires two more digital timers, one 8-bit (Timer_8 in DBB00) and one 16-bit (Timer_16 in DCB02 and DCB03). The software uses these timers for measuring intervals whose lengths are in the order of milliseconds. The clock comes from 3,750 Hz (VC3 = VC2/25) with a maximum count time of 68 ms and 17 s, respectively.

The LCD module occupies the I/O port 1. The quadrature encoder requires three additional I/O pins. I selected pins 0, 2, and 4 from port 2 because they are near each other on the Invention Board. Don’t forget to enable pull-ups on the encoder pins.