Issue
147 October 2002
12,
16, 18 Hike!
Dashing
for Flash
by
Jeff
Bachiochi
Whether
you’re gearing up to participate in the Microchip
2002 design contest or getting ready to follow the
action from your favorite recliner, now is the perfect
time to tune in for Jeff’s pre-game analysis.
Start
•
PIC18F252 •
Instruction Set •
Reset •
Serial
Port •
In-Circuit
•
Sources
& PDF
SERIAL
PORT
The
synchronous serial port (SSP) module can be configured
to support SPI or I2C. The SPI supports Master and Slave
modes. Master mode provides a synchronous clock out
to support data output and input pins. Slave mode accepts
a synchronous clock to support data output and input
pins. The clock comes from the system, prescaler, or
Timer 2.
The
I2C interface uses two bidirectional pins, data and
clock. In Master mode, a clock output is supplied and
data flows in and out of the data pin. In Slave mode,
the clock becomes an input and the data flows in and
out of the data pin. Multimaster mode allows masters
to compete for the bus, with the loser(s) of arbitration
allowing the winner to complete its message. The clock
for the I2C interface comes from a dedicated data rate
generator (BRG). This is an auto-reload 8-bit counter
with an optional divide-by-16 prescaler off of the system
clock.
The
universal synchronous asynchronous receiver transmitter
(USART) module can be configured for both sync and async
modes. Both modes use BRG as the clock source. Asynchronous
mode allows data to flow independently in both directions
(TX and RX) at the same time.
Because
Synchronous mode supplies a clock (by the master on
TX), data can flow only in one direction at a time on
RX. The data format is the same for both modes: 8(9)
data bits per byte, with the asynchronous mode requiring
one start and one stop bit per byte sent.
A/D
Between
the eight-channel multiplexer ahead of the 10-bit analog-to-digital
converter module and the ability to choose whether or
not pins are configured as digital, analog, or reference,
this module is highly user-friendly. Both the upper
and lower references for the analog-to-digital converter
can be configured for internal Vdd and VSS or external
voltages via port pins. This allows the input span to
be carefully tailored for maximum resolution. The 10-bit
A/D result can be right or left justified in the 16-bit
register pair, making it easy for a single-byte read
to retrieve the 8-MS or least significant bits of the
result.
It’s
recommended that the analog source impedance be less
than 2.5 kW. This will allow the converter to meet the
specified accuracy by permitting the internal sampling
capacitor to charge fully in a predetermined amount
of time (i.e., a minimum acquisition time).
After
a channel is selected, the application must wait this
acquisition time before beginning a conversion (setting
the GO bit in ADCON0). The GO bit will be cleared when
the conversion result is ready. You may wish to set
up CCPx and TIMER1 (or 3) to provide an acquisition
delay and automatic conversion start.
LOW-VOLTAGE
DETECTOR
When
using batteries, it’s often necessary to prepare the
application for shutdown by executing housekeeping tasks.
Sure, the brownout detector can stop execution before
things go haywire, but how do you prepare for this?
A
low-voltage detector can be set somewhere above the
brownout voltage so that it gives warning of impending
doom with time to make ready. The detector in the PIC18Fxx2
can be set to one of 14 levels or through an external
pin (LVDIN). These levels are tapped off of a voltage
divider powered by Vdd. The level is compared to a 1.2-V
internal reference also powered by Vdd. Therefore, the
LVDCON register has a bit (IRVST) that indicates when
you can trust the detector’s output and enable the interrupt.
WATCHDOG
TIMER
Watchdog
timers (WDT) are used to grab hold of an application
that’s executing errant code stuck in never-never land,
and then reset the system to regain control. The ’18Fxx2
has a watchdog timer that uses a completely autonomous
RC oscillator.
If
the device is configured with the watchdog enabled,
it can be arbitrarily enabled and disabled using the
SWDTEN bit in the WDTCON register. If it’s configured
as off, it cannot be controlled through software. The
nominal watchdog time out is 18 ms. A 7-bit postscaler
can extend this time to over 2 s if required. A WDT
overflow will reset the microprocessor. If it’s sleeping,
it will wake up and continue execution. To prevent the
WDT from timing out, the application must issue a CLRWDT
instruction periodically.
SLEEP
A
power-down mode is entered when the SLEEP command is
executed. The oscillator is stopped, but all I/O remains
in its present state. An MCLR will reset the micro,
but all of the other system events will wake up the
processor and restart the oscillator, allowing execution
to continue where it left off. Wake-up events can come
from WDT, INTx, RB, PSP, TMR1, TMR3, CCP, SSP, USART,
ADC, EEPROM/flash memory write, and LVD.
CODE
PROTECTION
The
code space within a PIC18Fxx2 is divided into blocks.
The first 0x200 bytes are considered the boot block,
and the following 0x1E00 bytes belong to block 0. The
remaining address space is divided into 0x2000 byte
blocks.
Each
block can be protected in three ways. The CPx bit prevents
the code from an associated block from being read by
an external source. Because code can be modified by
executing code, two additional protection bits are included.
The WRTx bit prevented a table write to an associated
block. The EBTRx bit prevents a table read from outside
of the associated block. Table reads within the block
are always allowed. Protection bits are enabled (cleared)
during the programming. After they’re programmed, protection
cannot be removed from any block unless the chip or
block is totally erased.
