Issue
147 October 2002
12,
16, 18 Hike!
Dashing
for Flash
Start
•
PIC18F252 •
Instruction Set •
Reset •
Serial
Port •
In-Circuit
•
Sources
& PDF
RESET
Numerous
sources can cause a reset, so knowing where the reset
came from can often allow an application to respond
differently based on the cause. Table 4 lists the functions
that can cause a reset.
| Table
4—There are several functions that can cause
a reset. |
To
ensure that the power supply and internal functions
have stabilized, special power-up delays are invoked
depending on the mode of the micro. If MCLR is tied
to VCC (i.e., no RC delay has been applied to the MCLR
pin), the power-up timer (PWRTE) can be enabled to hold
the micro in reset for an initial fixed 73-ms delay.
If a crystal or resonator is used, the micro is held
in reset for an additional delay of 1024 oscillator
cycles to ensure that the oscillator has stabilized.
When configured for PLL, the delay is extended for another
2 ms to allow the phase loop to fully lock.
When
enabled, the brownout detector can be set for one of
four voltages (2, 2.7, 4.2, or 4.5 V). Any time VCC
falls below this level, the micro is held in reset for
a total power-up delay after VCC has been restored.
On a wake-up from sleep or an oscillator source switch,
further execution can be delayed by 1024 oscillator
cycles plus 2 ms, depending on the mode.
HARDWARE
MULTIPLY
Math-intensive
applications can benefit from the hardware multiply
function included in the 18-series PIC processors. WREG
is multiplied by any 8-bit register to produce a 16-bit
result in a single instruction cycle. This unsigned
function saves about 68 instruction cycles over using
a software routine. For signed and other larger multiplies,
including the hardware multiply, the algorithm will
reduce execution time by a factor of seven to 15 times.
PORTS
Like
many micros, some port I/O pins are multiplexed for
alternate peripheral functions. Each port has three
registers associated with it. These registers are PORTx,
TRISx, and LATx (where x = A/B/C for the PIC18F2x2 and
D/E for the ’18F4x2).
The
TRISx register is a read/write register that determines
the direction of each port pin. When a bit position
equals one, the corresponding I/O pin is configured
as an input (high impedance). When a bit position equals
zero, the corresponding I/O pin is configured as an
output, and the logic level of the corresponding data
latch bit is placed on the I/O pin. Writing data to
the LATx or PORTx will update a data latch. Reading
the LATx register retrieves the present state of the
data latch. Reading the PORTx register retrieves the
present state of the port’s I/O pins (not the data latch).
Even
though it’s only available on the PIC18F4x2, which uses
PORTD and PORTE, the parallel slave port (PSP) is worthy
of being mentioned here. This peripheral allows the
micro to be interfaced directly to another processor’s
data bus. The 8-bit data port and three control signals
(CS, RD, and WR) camouflage it as a peripheral chip.
This little gem lets you design custom smart peripherals.
TIMERS
Four
16-bit counter/timers are included in the PIC18Fxx2
microcontroller. Each has several special features associated
with it. Timer 0 is selectable as an 8- or 16-bit timer
with appropriate rollover interrupt; it has a dedicated
8-bit prescaler and clock edge selection when clocked
externally.
Timer
1 and Timer 3 have dedicated 3-bit prescalers and clock
edge selection when clocked externally. Their clock
source can also come from the auxiliary low-power external
oscillator and synchronized to the system clock. Both
timers can be cleared by a trigger from the CCP module
(Compare mode).
Although
Timer 2 has an 8-bit timer register (TMR2), it can achieve
a 16-bit count with the 4-bit prescaler and 4-bit postscaler.
A second 8-bit period register (PR2) is compared to
the TMR2 and used as a reference. When the registers
match, the TMR2 register is cleared (data rate generator).
Prescalers
are normally cleared with a write to the lower byte
of any timer.
CCP
Each
PIC18Fxx2 contains two identical CCPx modules (where
x = 1 or 2). In Capture mode, a 16-bit timer count (Timer
1 or Timer 3) is transferred into a 16-bit CCPRxH/L
register pair on a selected event. An event is defined
as every falling edge, every rising edge, every fourth
rising edge, or every sixteenth rising edge.
In
Compare mode, the value in the 16-bit CCPRxH/L register
pair is compared to a 16-bit timer count (Timer 1 or
Timer 3). A match initiates an interrupt and triggers
a clear to the counter/timer. A match can also toggle
an output pin or produce a rising or falling edge on
a match.
Timer
2 is used for the PWM period timer servicing both PWMs.
When implemented as the PWM period timer, two additional
least significant bits are used, either from the Timer
2 prescaler or the Q clock when the prescaler is 1:1,
to produce a 10-bit value. When Timer 2 matches (TMR2
= PR2), TMR2 is cleared, the CCP output pin is set,
and a CCP reload is triggered. The duty cycle period
is determined by the 8-bit value in CCPRxL + 2 bits
from the CCPxCON register. This 10-bit reference value
is loaded into the 8-bit CCPRxH + 2-bit internal latch
by the Timer 2 trigger. This 10-bit value is compared
with Timer 2’s 10-bit register (TMR2 + 2 bits). A match
between these 10-bit registers clears the CCPx output
pin.
So,
the period equals the amount of time it takes TMR2 to
count up to PR2. The on (i.e., CCPx output pin is high)
time is the time it takes TMR2 to match CCPRxH. If the
CCPRxH is zero, the output never gets set. If CCPRxH
is greater than TMR2, the output never gets cleared
because CCPRxH will never match TMR2.
