Issue 147 October 2002
12, 16, 18 Hike!
Dashing for Flash

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Start • PIC18F252 • Instruction Set • Reset • Serial Port • In-Circuit • Sources & PDF

INSTRUCTION SET

Instructions are grouped into five categories: byte-oriented, bit-oriented, literal, control, and table-oriented. The byte-oriented operations are listed in Figure 3. They contain an opcode and up to three operands: a file register (f), a destination bit (d), and a RAM access bit (a).

The file register is the location in a RAM bank on which the operation is to be performed. The destination bit indicates where the result of the operation will be placed. When d = 0, the result goes into the WREG. When d = 1, the result is put back into the file register. The RAM access bit indicates where the file register will be found. When a = 0, the file register is taken from the access register bank. If a = 1, the file register is taken from the RAM bank indicated by the BSR. Note that this is a source of confusion, so it must be chosen wisely.

For instance, if the file register of interest is the SFR TXREG, you may use a = 0 to indicate it’s in the access bank. If the BSR = 0x0F, you may use a = 1, otherwise using a = 1 (RAM bank) when BSR points to any other bank will make use of the wrong register (see Figure 2).

(Click here to enlarge)

Figure 2—Data memory is divided into 256-byte static RAM banks. Data addressing is available via the access bank or through the bank select register (BSR). The BSR’s lower nibble selects one of the 16 RAM banks (0 to 15). The access bank is always available. It consists of the first half of RAM in bank 0 plus the special function registers (SFR) in the last half of bank 15.

Most byte-oriented instructions are single-word instructions that execute in a single instruction cycle (except where the PC is altered). In the byte-oriented category, there’s also a register-to-register move, which requires two words because it’s a direct move avoiding the use of bits a and d. As such, it must contain the 12-bit address of each register. This instruction takes two instruction cycles to execute.

The bit-oriented instructions are listed in Figure 4. These contain an opcode and three operands: a file register, a bit position (b), and a RAM access bit (a). The file register is the location in a RAM bank on which the operation is to be performed. The bit position specifies on which bit (from 0 to 7) the operation is to be performed. The RAM access bit indicates where the file register will be found.

When a = 0, the file register is taken from the access register bank. And when a = 1, the file register is taken from the RAM bank indicated by the BSR. All bit-oriented instructions are single-word instructions and execute in a single instruction cycle (except where the PC is altered).

The literal instructions are listed in Figure 5. These contain an opcode and one or two operands: a constant (k) and an FSR (f). In most cases, an operation is performed using an 8-bit constant and the WREG, with the result being placed back into the WREG. One instruction uses an FSR to point to one of the three indirect file register sets, which will accept the 12-bit direct RAM memory address (k). This move is a two-word instruction requiring two instruction cycles.

Control operations have to do with instructions that can change the path of execution. These contain an opcode and up to two operands (see Figure 6). Opcodes without operands have direct operations like CLRWDT (clear watchdog timer), NOP (no operation), and SLEEP (go into a Standby mode). There are both direct and relative GOTO (BRA) and CALL (RCALL) instructions. The direct instructions require two words. Because all of them affect the PC, they all require two execution cycles. Even though all conditional branch instructions are single words, they too affect the PC, and as such, they require two execution cycles.

The eight table operations were discussed earlier and are listed in Figure 7.

INTERRUPTS

If you’ve worked with the 12-bit PICs, then you know it’s not easy coding without interrupts. Even with the advent of interrupts, many applications suffer from long interrupt latencies (i.e., the time from the initial interrupt event to the time when the interrupt is actually serviced). This might be the result of having to save registers, poll the interrupt register, or another interrupt routine having control at the time. The 18-series micros have a number of latency-reducing features.

The first is two levels of priority. Often, your project will include more than one interrupt routine. When all of the interrupts are equal, a pending interrupt must wait for any in-process interrupt to complete. Eighteen-series interrupts can be optionally defined as either high or low priority (see Table 3). Each priority has a separate interrupt vector address. A high-priority interrupt can interrupt a low-priority interrupt immediately. Therefore, a high-priority interrupt has the lowest interrupt latency.

An interrupt automatically saves the WREG, STATUS, and BSR bits into a one-level fast stack. The control instruction RETFIE (return from interrupt) has an s operand that controls whether or not the return from the interrupt is with or without restoring these registers from the fast stack. Care must be used because the fast stack is only one level. If a high-priority interrupt interrupts a low-priority routine, the low priority’s automatic save is overwritten when the high-priority interrupt begins. The control instructions CALL and RETURN also have the s operand and can make use of the fast stack, but should be used only if interrupts are disabled or not used.

CLOCK OSCILLATOR

The PIC18Fxx2 micros support eight oscillator modes. The low-power (LP) mode supports crystals up to 200 kHz. Crystals or resonators up to 4 MHz can be used with XT mode. For frequencies up to 20 MHz, the high-speed (HS) mode is used.

To reduce EMI, the PLL mode accepts crystals or resonators up to 10 MHz and internally multiplies them by four. These modes require both OSC1 (input) and OSC2 (output) pins. The RC resistor/capacitor (RC) and external clock (EC) modes require only the OSC1 input. The OSC2 output will have a clock output derived by an OSC1 divided by four. Alternatively, the OSC2 output can be disabled and the pin used as an extra I/O with RCIO and ECIO modes. Timer 1 can be configured as a low-power clock by attaching a 32-kHz watch crystal to its oscillator pins. The system clock can be sourced and switched between either of these oscillators, making for some rather interesting speed/power trade-offs.