Issue
147 October 2002
Design
with STKxxx
Build
an Ethernet Controller
BOARD
MEETING
Now
that you’re familiar with all of the development boards,
let’s put them together and explore the AX88796’s internals.
Of course, I always begin with a smoke test. In my haste,
I attached the AX88796 development board to a 5-V VTG
STK500/ STK501 system. To my amazement, nothing was
damaged on the AX88796 development board. That was a
good omen.
According
to the AX88796’s datasheet, you should be able to port
NE2000-compatible code to the AX88796 with little pain
and no tears. I’m going to test this because I plan
to use much of the same code that the now world-traveled
RTL8019AS-based Packet Whacker (it’s also hooked up
to a web cam) employs.
After
reviewing the datasheet for the AX88796, I determined
that I had to make some minor changes in the MAC register
definitions. I also had to add some definitions because
the AX88796 includes registers and bits that the RTL8019AS
does not have. The MAC core register set is identical
in the buffer ring control areas. The same page start,
page stop, current page, and boundary registers described
in the National Semiconductor documents exist on the
AX88796. The SRAM buffer area is also mapped to the
standard NE2000 location of 0x4000 through 0x7FFF. I
was pleasantly surprised by the inclusion of content
in the AX88796’s datasheet that is similar to the original
National Semiconductor datasheet content describing
the ins and outs of using the buffer ring and DMA resources
of the NIC.
Unlike
the RTL8019AS, there are no pages two and three of the
AX88796 MAC register set. That’s because the EEPROM
is not automatically accessed, so there is no need to
reserve space for that "expected" data. Also,
Duplex mode is easily selectable using bits in the transmit
configuration register (TCR) in the MAC/MII register
area. The RTL8019AS contains this mode and the LED activity
mode stuck in a hard-to-reach page-three area of the
MAC. The LED mode for the AX88796 is pin-selectable
by using the I_OP pin of the AX88796.
A
notable difference between my original Packet Whacker
code and the AX88796 ported code is the way the AX88796
handles NIC reset. The RTL8019AS uses the interrupt
status register (ISR) RST bit to indicate when the NIC
is out of reset. The AX88796 RST bit is simply an indicator
that is set when reset is entered; it’s cleared when
a start command (0x22) is issued to the command register
(CR).
There
are many other interesting ways to monitor reset on
the AX88796. To accomplish this, the AX88796 adds a
test register (TR) at MAC register offset 0x15. Within
the TR register are four bits: 100BASE-TX in reset,
10BASE-T in reset, Reset Busy, and Auto-Negotiation
Done. Some of the reset results are based on the auto-negotiation
process. Reset Busy or RST_B is the replacement for
the RST bit in the ISR, and it indicates whether or
not the AX88796’s PHY is in reset. Because the AX88796
can operate in 10BASE-T or 100BASE-TX mode, the PHY
contains logic for both modes with the modes being mutually
exclusive.
Auto-negotiation
is a means of establishing the highest performance link
between stations on a network. For instance, if a station
on a network can operate only in 10BASE-T Half-Duplex
mode, the auto-negotiation process determines this and
sets up the link accordingly. Each node knows about
the other through advertisements of each node’s abilities.
These advertisements are transmitted using fast link
pulses, or FLPs. An FLP burst contains 33 link pulses
that occur at the same intervals as 10BASE-T normal
link pulses (NLPs).
NLPs
occur every 16.8 ms. Each FLP burst is 100 ns wide.
FLP bursts interleave clock pulses with data pulses.
The 17 odd link pulses are clock pulses, and the 16
even link pulses are the data. The absence of a pulse
following a clock pulse encodes a logic 0. Conversely,
a pulse within the time window following a clock pulse
encodes a logic 1. This invisible encoding process ultimately
becomes a 16-bit word or link-code word (LCW). Bits
within the LCW represent the abilities of the nodes
that are establishing the communications link. Using
the datasheet, you can see the AX88796’s abilities listed
in the MR1 register of the AX88796’s embedded PHY register
set.
I
wrote some simple code to read the TR register bits
and connected the AX88796 development board to a 10BASE-T
network. After performing an NIC reset, reading the
TR register indicated that the 100BASE-TX logic was
in reset. I then connected the AX88796 development board
to a 100BASE-TX network and performed a NIC reset. Just
as I expected, the 10BASE-T logic was in reset when
connected to the 100BASE-TX network. In both cases,
the PHY reset bit was set and later cleared, indicating
that the PHY reset successfully. So far, so good.
Although
accessing the MII is not required, I thought that it
would be a good idea to have AVR code to read and write
the AX88796’s embedded PHY registers. As it turns out,
if I want the AX88796 to behave, I must be able to write
to the MII’s MR0 control register. There’s a statement
in the datasheet that basically says you must put the
AX88796’s embedded PHY in Power Down mode for 2.5 s,
and then restart the auto-negotiation process to assure
that a good link is established. To do this, you must
write two sequences to the MR0 embedded PHY register.
This brought about the addition of another MAC register,
the MII/EEPROM Management Register (MEMR), at offset
0x14, to my original MAC definitions.
The
MEMR register is the origin and endpoint of data going
to and from the AX88796 embedded PHY and the external
8-pin EEPROM. The upper four bits of the MEMR represent
all of the EEPROM signals—EECLK, EEO, EEI, and EECS.
The lower nibble of the MEMR is dedicated to the MII
interface. Follow along using Figure 1 as I describe
how to interface with the AX88796’s embedded PHY.
|
(Click
here to enlarge)
|
Figure
1—Although I slowed the clock to 1-s intervals to
watch the LEDs, this interface can run at 12.5 MHz
against the internal PHY. |
Notice
that pins 66 and 67 can be used to communicate with
an external PHY. These pins also can be used during
debugging. I connected them to a couple of LEDs on the
STK500. The clock for the communications session is
provided by alternately loading the MDC bit (bit 0)
of the MEMR with a one and zero. I slowed down this
clock to 1-s intervals in order to observe the clock
and data activity on pins 66 and 67. Everything is synchronized
to the rising edge of the MDC clock pulse.
So,
to send a one to the embedded PHY, simply set the MDO
bit (bit 3 of the MEMR) and write a one-zero sequence
to the MDC bit location. To read a bit from the PHY,
you must clock the MDC bit and check the status of the
MDI (bit 2) bit of the MEMR. The secret to success,
when reading and writing the embedded PHY, is to know
that it’s addressed as 0x10.
The
bottom of Figure 1 contains the frame format used to
communicate with the embedded PHY. The preamble is not
required because a bit (bit 6) is set in the MII MR1
register to bypass it by default. A simple start-of-frame
sequence is clocked in (ST) followed by the read/write
opcode (OP). The bits are clocked in just as you see
them, from left to right.
So,
to talk to the embedded PHY, 10000 is clocked in as
the PHY address. There are 5 bits in both the PHY address
(PHYAD) and PHY register address (REGAD). This allows
32 PHY addresses to be defined, and it gives access
to 32 registers within each of the 32 PHYs. Note that
a PHY address of 0x10 muxes the embedded PHY’s output
to the MEMR. Any other PHY address would mux the input
from pin 66 into the MEMR. The GPO and Control (GPOC)
register (another addition to the MAC register definitions)
allows you to choose between an external and the internal
PHY. The AVR code to access the embedded PHY is shown
in Listing 1.
REGISTER
TO WIN
It’s
pretty obvious that you can easily control the AX88796
if you know how to manipulate its registers. I also
added the SPP Data Port Register (SPP_DPR) at offset
0x18, the SPP Status Port Register (SPP_SPR) at offset
0x19, and the SPP Command Port Register (SPP_CPR) at
offset 0x1A to support bit banging from the AX88796’s
bidirectional I/O printer port.
You
may download the complete AX88796 AVR code from the
Circuit Cellar ftp site. For more information about
the AX88796 development board, head over to the EDTP
Electronics web site (www.edtp.com).
Now
that you know how to read and write the AX88796’s MAC
and MII registers with an ATmega128L, you too can be
on your way to building a 100-Mbps Ethernet using an
8-bit AVR microcontroller, proving along the way that
it doesn’t have to be complicated to be embedded.
