Issue
147 October 2002
Design
with STKxxx
Build
an Ethernet Controller
DRIVING
THE TOOL SET
The
STK500, STK501, and JTAG ICE all are designed to be
driven using hooks in Atmel’s AVR Studio. After connecting
the STK500/STK501 hardware to my PC’s serial port, I
downloaded the latest version of AVR Studio from Atmel’s
web site. After discovering the STK5xx hardware, AVR
Studio requested that I update the STK500’s firmware
to enable the enhancements offered by the new version
of software. Likewise, AVR Studio performed a similar
upgrade to the JTAG ICE firmware.
I’m
in the process of evaluating a new Ethernet IC from
ASIX. The part I’m looking at is the AX88796 three-in-one
Local Bus Fast Ethernet Controller. I will need a minimum
of three of the ATmega128’s I/O ports to provide address,
data, and control signals for the AX88796. The port
set included with the STK500 becomes an extension of
the ATmega128 port set when the STK501 daughterboard
is attached. This gives you I/O ports A, B, C, and D
on the STK500, and I/O ports E, F, and G on the STK501.
Each port is pinned out identically (i.e., pin 1 of
the I/O port header is bit 0, pin 2 is bit 1, and so
forth). This consistent pinout allows for the use of
simple 10-pin female-to-female ribbon cables as the
I/O signal carriers between the STK boards and between
the STK boards and external hardware under development.
To
complement the services provided by AVR Studio, I will
be using the ImageCraft ICCAVR Professional C compiler
to produce the firmware for the new Ethernet IC. Because
I will be porting code in the Ethernet application,
I don’t plan to employ the services of the JTAG ICE
unless things get really sticky. I’ll debug using the
second serial port of the ATmega128L running at 57.6
Kbps. The pins for the primary serial port will be used
for ISP (in-system programming). I’ve already written
a module that will allow me to use printf statements
aimed at the secondary serial port. According to the
AX88796 datasheet, the AX88796 is compatible with the
NE2000 register set, which means I can use most of the
same code that makes the RTL8019AS-based Packet Whacker
hum. [1]
OK,
it looks like I now have all of the necessary AVR tools
assembled on the bench to begin working with the AX88796.
The next step in the process is to gain easy access
to the 128 pins that hang off the AX88796 LQFP package.
DEVELOPMENT
BOARD
The
AX88796 development board is designed to be easily interfaced
with the Atmel STK500 and STK501 AVR development boards.
All of the AX88796 development board’s address, data,
and control lines are pinned out to 10-pin male headers.
The pinout of the AX88796 development board headers
matches the header pinout pattern of the STK boards.
In addition to providing a means of easy access to digital
signals on the development boards, each male header
includes pins that transport power and ground as well.
Pin 9 is ground; pin 10 is VTG (V Target).
The
AX88796 is a 3.3-V part with 5-V tolerant I/O. Therefore,
a couple of things must happen on the STK500/ STK501
end to accommodate this. First, the STK500 AVR target
voltage (VTG) must be set for 3.3 VDC in AVR Studio.
Second, the standard ATmega128-16AC must be replaced
by the ATmega128L-8AC because the ATmega128-16’s operating
voltage range is 4.5 to 5.5 VDC. The L version of the
ATmega128 extends the voltage range down to a 2.7-VDC
minimum.
Another
trade-off for moving to the L version of the ATmega128
is that the maximum clock speed decreases from 16 to
8 MHz. Neither the need for the L version of the ATmega128,
the 3.3-VDC operating voltage, nor the microcontroller
speed is a showstopper with the STK500/STK501 tool set.
Even at 8 MHz, the ATmega128L is speedy, and the 8-MHz
speed limit is more than fast enough for this application.
In fact, I’ll use a 7.3728-MHz crystal to clock the
ATmega128L. That’s as close to 8 MHz as I can get and
still clock the data rate generator accurately.
Obtaining
the 3.3 VDC for the AX88796 is as simple as a mouse
click inside AVR Studio. The spring-loaded ZIF allows
the ATmega128 to be replaced by an ATmega128L in seconds.
As
you can see in Photo 4, the AX88796 development board
has four 10-pin male headers. One header pins out five
of the AX88796’s 10 address lines. The lower five address
lines are used to access the AX88796’s internal NE2000
(MAC) register set. The remaining address lines are
hardwired to a base address of 0x200, which is the default
base address for the AX88796. Using the default address
allows the three base address pins (i.e., I/O_BASE[0],
I/O_BASE[1], and I/O_BASE[2]) of the AX88796 to be left
unconnected and follow their internal pull-up and pull-down
circuitry. The address header also pins out the *IORD
and *IOWR I/O control signals and the interrupt request
line (IRQ).
|
(Click
here to enlarge)
|
Photo
4—Every pin that isn’t tied to a power rail is pulled
out to the header pins. Because I’m new to this
IC, I wanted everything to be accessible. |
The
ATmega128 is an 8-bit microcontroller, and the AX88796
is designed to run in 8- or 16-bit mode. So, there is
a header for the lower eight data bits and another for
the upper eight data bits of the AX88796. Data bits
8 through 15 are pinned out on the AX88796 development
board for those of you who want to operate in 16-bit
mode. Setting a bit in the AX88796’s data configuration
register (DCR) selects 8- or 16-bit mode.
The
fourth header contains pins for the ISA mode AEN and
RDY signals. The AX88796 is billed as a Local Bus Ethernet
Controller, and CPU[0] and CPU[1] pins on the AX88796
can be configured for one of four local bus CPU modes.
These modes include ISA, 80186, 68K, and 8051. The AX88796
pins morph with the CPU selection. For instance, in
8051 mode, the AEN pin becomes the PSEN signal. When
the CPU[X] pins are jumpered for 68K mode, the RDY line
becomes the DTACK line and address line SA[0] doubles
as the LOWER DATA STROBE (LDS) signal. AX88796 chip
select (CS) and RESET can be accessed on the header.
To accommodate 16-bit designs, the BUS HIGH ENABLE (BHE)
signal is also pinned out to this header. AX88796 CS
also can be permanently enabled with a jumper or controlled
by the AVR at the header.
In
addition to being a 10/100-Mbps Ethernet controller,
the AX88796 can be configured to interface to a printer.
All of the standard printer control lines, including
a bidirectional data bus, are pinned out on the AX88796
development board. These lines double as media-independent
interface (MII) signals by default. When MII signals
are activated, an external PHY can be accessed to implement
other types of networks. In either mode, special-purpose
registers inside the AX88796 manipulate the feature
signals.
Moving
to the opposite side of the printer interface pins,
you can see a socket area for an 8-pin EEPROM. Unlike
the RTL8019AS, the AX88796 does not automatically look
for this EEPROM at power-up. Instead, the EEPROM is
placed under your control, and it’s accessed with an
internal AX88796 EEPROM register set.
The
AX88796 development board’s magnetics are housed within
the NU1S041C-434 Lan Mate. The NU1S041C-434 complies
with the IEEE 802.3u standards. The Lan Mate is configured
with a 1:1 center-tapped turns ratio, and it incorporates
all of the necessary electronics to interface to the
in-can RJ45 connector.
In
addition, the NU1S041C-434 includes three in-can status
LEDs. You may download a diagram of the NU1S041C-434
from the Circuit Cellar ftp site (it’s included in the
schematic for the main AX88796 development board).
