Issue
146 September 2002
Killing
the EMI Demon
by
Norman Rogers
Reduction Trick #3
A line spectrum is the
spectrum generated by a square wave clock or by a train
of short pulses. All of the energy is concentrated in
a narrow spectral line at the harmonic frequencies.
When the FCC EMI measurement
tests are performed, the spectrum analyzer measures
the amplitude of the signal from a 120-kHz wide filter
that is swept across the frequencies of interest. With
a line spectrum, all of the energy in a single line
passes through the filter, resulting in a strong signal.
If the energy in the line could be spread out over a
wider frequency, say 5 MHz, only one-fortieth the energy
would pass through the 120-kHz wide filter, considerably
reducing the reading (by 16 dB in amplitude for one-fortieth
of the energy). This is what a clock spectrum spreader
does. It modulates the clock frequency by a little so
as to smear out the spectral line in frequency. The
idea to do this for the purpose of reducing EMI was
patented by Bell Labs in two patents during the 1960s.
There are numerous ways
to modulate the clock frequency. One method is to use
a voltage-controlled oscillator and phase-lock loop
so that the frequency sweeps back and forth at a low
modulation rate (e.g., 50 kHz). Another method is to
insert random delays or dithers into the clock. These
methods are all covered in the original Bell Labs patents.
The Bell Labs people were probably interested in EMI
because telephone switches involve a large amount of
equipment in a small space. In addition, it’s conceivable
that the early computerized switches suffered from EMI
problems.
We installed a clock spectrum
spreader in the Rabbit 3000 based on a combination of
digital and analog techniques. The spectrum spreader
reduces FCC-style EMI readings by around 20 dB, which
is a lot.
A control system makes
sure that the modulated clock edge is never in error
by more than 20 ns compared to where the clock edge
would be if it were not modulated. This prevents disruption
in serial communications or other timing functions.
For example, a UART operating at 460,000 bps can tolerate
about 500 ns of clock edge error before it will be near
to generating errors. This is far less than our 20-ns
worst error in clock edge position.
