Issue
109, August 1999
Using
System-on Chip Design with Virtual components
VC Verification
Issues
One area common
to both single-VC and multiple-VC SOC designs is the
need to verify and test the complete chip. The SOC design
and test engineers want to leverage and build on the
verification and test done for each individual VC, and
accordingly they expect the VC provider to assist in
this process.
As previously
noted, each VC is accompanied by some sort of simulation
model that enables the SOC designer to run chip-level
tests that involve the VC. But, that doesn’t provide
any support for determining whether the VC is connected
properly in the design and is operating correctly in
the context of the full SOC. A VC with a miswired application
interface will simulate, but the results may not be
correct.
Figure 4—A
verification environment provides behavioral models
and test scripts to verify the functionality of
the VCs. This approach can be used in full SOC
verification as well as stand-alone VC verification.
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Many suppliers
address this problem by providing a verification environment
along with the VC itself. Such an environment provides
behavioral models (usually in Verilog, VHDL, or C) that
interact with the VC and a set of test scripts that
use these models to verify the functionality of the
VC. Figure 4 shows a sample verification environment
for an interconnect VC such as PCI or 1394. Key components
of this approach include:
• master
model to address the VC as a target
• target
model to respond to VC as a master
• sample
application code to stimulate VC
• tests
written as scripts of procedural calls
• monitors
for protocol and timing correctness
As a stand-alone
test for the VC, a verification environment lets you
verify a postsynthesis netlist or a customized version
of the VC to ensure that protocol and timing rules are
satisfied. A simple set of test vectors performs much
the same function for stand-alone VC verification, but
debug is harder without monitors and readable test scripts.
One of the
main advantages of the verification environment approach
is that many of its components can be used in the full
SOC verification in addition to the stand-alone VC verification.
The master and target models can be connected to the
SOC bus interface while the protocol and timing monitors
can continue to be used.
It may be
possible to continue to run the same test scripts on
the SOC, requiring the chip designer to modify the procedural
interface to stimulate the VC from the actual SOC logic
rather than from the sample application.
A verification
environment can be provided with any VC, whether in
hard or soft form. Synthesizable-VC suppliers usually
provide verification environments and hard-macro suppliers
often provide some components such as bus models to
aid in SOC verification.
Many of these
components are useful to a designer developing a custom
implementation of an interface or processor. So, it’s
quite common for IP providers to license a verification
environment even to customers who do not license the
VC itself.
