Issue
97, August 1998
Designing
for Smart Cards
- Part 2: Practical Implementation
PHYSICAL
CONSIDERATIONS
To
implement a smart-card system, first consider the size
of the pertinent changing data, which will be in the
EEPROM, and the size of the application software or
OS, which is implemented in ROM. Both are commonly touted
features of smart-card vendors.
The
price of the silicon is proportional to the EEPROM array,
but like other devices, smart cards are evolving into
larger EEPROM array sizes and cheaper prices. Most vendors
are currently using 0.6–0.8-mm geometries and die
with areas less than 25 mm2.
The
physical resources of the silicon should be carefully
considered when developing the functions of the OS or
application software. Specifically, think about the
RAM.
How
many levels deep will subroutines or interrupts go into
the stack? If software doesn’t use the entire stack,
those free RAM bytes are available to the OS.
Cryptographic
algorithms use large amounts of RAM, affecting the selection
of silicon (and the algorithm), as well as the number
and size of pertinent RAM variables. The I/O buffer
of received and soon-to-be transmitted data is likely
to consume the most RAM.
