COG IN THE MACHINE

For now let’s keep it simple by getting to the core of the matter. Dig deep enough into the silicon and you’ll find a so-called “cog” consisting of a tiny 32-bit processor with 2 KB (512 32-bit long words) of RAM and a dash of specialized video/timer hardware.

The cog itself is an interesting mix of RISC, CISC, and every other kind of ’ISC you can think of. Conventional machines differentiate between registers and memory and code and data. By contrast, with the cog, everything lives in the 2-KB RAM. And while there are only 64 opcodes in the instruction set, many the usual suspects, there are a number of unique embellishments. For instance, every instruction features conditional execution based on the state of the zero and carry flags. This supports deterministic straight-line coding instead of jittery conditional branches.

Similarly, but on the other side of the coin, writing the results (flags, destination register) of instruction execution is also an option. In a sense, the conditional execution and optional result writing mean the chip really has 8,192 instructions (i.e., 6-bit opcode + 4-bit conditional execution + 3-bit optional result writing), although many permutations would be of dubious use.

An interesting point about the stack is that there isn’t one. Instead, the cog takes advantage of the fact that instructions are in RAM to emulate a conventional processor’s stack-based CALLs and RETURNs by jamming the appropriate addresses into a JMP instruction at run-time (i.e., self-modifying code).

The video/timer stuff is pretty black magic, going well beyond the simple units found on typical MCUs. Suffice it to say that the two 32-bit counters with dedicated PLLs and video shifter can do very interesting things (e.g., audio and video) very quickly and very precisely. Each counter uses zero, one, or two pins depending on which of its 16 operating modes is selected.