August
2004, Issue 169
PSoC
101
PSoC
BASICS
There
are numerous PSoC variants that contain differing combinations
of internal resources and I/O pin counts. Because my
PSoC development system is geared toward the 28-pin
CY8C27443, that’s the part I’ll concentrate on in this
column. After you have the CY8C27443 fundamentals down,
you can use the same concepts to design with the other
members of the CY8C27XXX family.
The
CY8C27443 is composed of an 8-bit microcontroller core,
eight 8-bit digital PSoC function blocks, and 12 analog
PSoC function blocks. The eight 8-bit digital PSoC function
blocks are divided into a group of four digital basic
blocks (DBBXX) and a group of four digital communications
blocks (DCBXX). Each PSoC function block, analog and
digital, is programmed at the functional level. That
means that any of the eight 8-bit PSoC digital function
blocks can be defined as timers, counters, PWM generators,
or random sequence generators.
The
PSoC digital basic blocks cannot be used to implement
UART, I2C, SPI, IR, or CRC functions. PSoC digital communications
blocks only perform the aforementioned digital communications
functions. These predefined and precharacterized functions
that transform the PSoC function blocks into digital
and analog subsystems are called user modules.
Don’t
worry about trying to remember what does what and what
goes where as far as the PSoC function blocks and user
modules are concerned. The PSoC Designer IDE won’t let
you place a user module in the incorrect PSoC function
block. In addition, you don’t have to worry about coding
at low levels to get the PSoC function block and user
module to interoperate. The base driver code for the
predefined PSoC user module is automatically generated
when you place a user module into a PSoC function block.
An API supports each user module. The API gives you
access to the PSoC register set and functions that are
associated with the user module.
As
you might imagine, digital function blocks can be attached
to PSoC I/O pins, other PSoC digital function blocks,
PSoC clock sources, and PSoC analog function blocks.
The interconnections are defined by using the PSoC Designer
IDE. I placed an 8-bit counter in DBB00 and a 16-bit
counter in PSoC digital basic blocks DBB10 and DBB11
(see Photo 1). PSoC Designer automatically places a
selected user module in the next available function
block, so I purposely overrode the PSoC Designer’s placement
automation and placed the 16-bit counter at DBB10 and
DBB11 to preserve the DCB02 communications block for
use by communications-oriented user modules. Refer to
the Circuit Cellar ftp site for additional photos.
|
(Click
here to enlarge)
|
Photo
1—Note that a 16-bit PSoC counter requires two PSoC
digital function blocks. I tied the counter enable
lines high to make them active. The lines also can
be controlled by outputs from the comparators, input
I/O pins, or output I/O pins. Each of the little
blue output and red input muxes covers four of the
16 green vertical global interconnect lines. |
After
a user module is placed in a function block, the logical
connections and parameters are defined (clocking, interrupts,
gain, references, etc.), and any desired inter-function
block data paths and I/O pin connections are established.
Photo 1 looks pretty busy, but the PSoC user module
placement and connection process is extremely intuitive.
You can click on the objects to select connections,
or you can make connections by choosing from choices
offered in the user module Parameters window.
The
PSoC analog function block area of the CY8C27443 is
composed of 12 PSoC analog blocks arranged in four columns.
Each PSoC analog block column includes a continuous
time analog block (ACBXX), a switched capacitor C analog
block (ASCXX), and a switched capacitor D analog block
(ASDXX).
ACBXX
PSoC analog blocks are made up of a rail-to-rail, low
offset/low noise op-amp and include a register-bit-setting
controlled precision resistor network in the op-amp’s
feedback path. A couple of obvious uses for the ACBXX
analog blocks include the realization of the programmable
gain amplifier (PGA) user module and the programmable
threshold comparator user module. Adding a classic op-amp
configuration to a PSoC design is absolutely “no problem.”
DACs,
filters, and ADCs are built from the switched capacitor
analog blocks, ASCXX and ASDXX. Like the ACBXX PSoC
analog blocks, the ASCXX and ASDXX analog function blocks
are built around a rail-to-rail, low-offset, low-noise
op-amp. They also depend on register values to determine
the relative weights of the switched capacitor arrays
that are muxed to the op-amp’s input and output.
There
are four switched capacitor arrays in each respective
set of ASCXX and ASDXX switched capacitor analog function
blocks. Arrays A, B, and C are input arrays. Switched
capacitor array F is in the op-amp feedback path. The
difference in the two switched capacitor analog blocks
is in how the C array is configured and the extended
amount of switching control offered on the B input array
of the ASDXX analog block.
I
placed a quad of PGA user modules in the CY8C27443’s
analog block space (see Photo 2). You can’t click on
Photo 2 to see the multiplexer names and choices, so
let’s work the PSoC analog subsystem from the top muxes
down.
|
(Click
here to enlarge)
|
Photo
2—This is where you want to click to your heart’s
content. Although it isn’t shown in this shot, the
PSoC Designer IDE provides a list of connect points
and optionally can physically point them out to
you. This shot looks busy, but in reality, it’s
all extremely logical. After you click on the muxes
and see the paths change before your eyes you’ll
know what I mean. |
The
two topmost eight-input multiplexers above the four
analog function block columns are analog clock select
muxes. The clock sources for these muxes encompass clock
outputs from all eight of the DBBXX and DCBXX digital
function blocks. The next row of four-input muxes selects
the PSoC device input I/O pin that will feed the PSoC
analog column that the column’s input mux’s output is
connected to. From left to right, the first and third
four-input muxes tie in odd numbered Port_0 I/O pins.
The second and fourth four-input muxes bring in the
even numbered Port_0 I/O pins. The two center column
inputs have an additional pair of two-input muxes, which
allow the columns to be connected either to even or
odd numbered Port_0 I/O pins. The lowest set of four-input
muxes selects a clock source for the PSoC analog block
column it supports. All of the configuring is done simply
by clicking on the mux and selecting a PSoC pin, connection,
or clock source.
In
the Photo 2 example, I connected the PGA outputs to
PSoC Port_0 I/O pins using the four output buffers.
However, I can also connect the PGA outputs to other
PSoC analog block inputs instead if my application demands
it. Each column’s analog blocks have access to the analog
out bus that feeds the column buffers.
Each
PSoC analog block column also has access to a comparator
bus whose outputs can feed user module inputs in the
digital function block space. I connected the first
PGA user module output to the input of the 12-bit A/D
converter user module below it in the ASC10 position.
The A/D converter is connected to Comparator0, which
can feed a timer or counter input in the digital area
if required.
The
PGA user module’s gain can be set in the user module
Parameters window or via the PGA user module API. The
A/D converter is also controlled by an API, which allows
for starting, stopping, and gathering data from the
A/D converter user module.
I
think you’ve got the general idea of how things work
inside a PSoC device and the role the PSoC Designer
plays in the development process. So, let’s move on
and look at the actual hardware and firmware behind
the pretty pictures.
