Issue 157 August 2003
Spotlight on Renesas H8 Family
Hitachi and Mitsubishi Market MCUs for Embedded Systems

H8/300H SERIES

The H8/300 series has a 32-bit architecture similar to the H8/Tiny; however, with a 64-KB address space, the ’3048 can make full use of the 23-bit PC and 16-MB address. The address space can be divided into eight areas, each with separate bus specifications. Enhanced addressing and instructions help make full use of the address space and 32-bit data registers. A 16-bit DRAM controller has multiple refresh modes. A direct memory access (DMA), integrated timer unit (ITU), and timing pattern controller (TPC) were added to the standard UART, ADC, and DAC peripherals.

The ’3048 series handles apps that require additional processing power. It’s useful for HVAC, AC motor control, color copiers, and diagnostic equipment.

The DRAM controller produces the CAS and RAS signals in support of 8- or 9-bit column address multiplexing. The on-board bus controller allows external devices requiring different bus specifications to live in harmony by segregating them into one of eight address areas. Each area can have specific wait states generated for them.

The bus master also arbitrates bus rights between the CPU, DMAC, refresh controller, or an external bus controller. The DMAC transfers up to 64 KB of byte/word data one time in a block move (or to the same address), or it repeats the operation continuously.

DMA Short mode uses an 8-bit source and 24-bit destination. Long mode uses a 24-bit source/destination. The DMA has resources for four short or two long DMA channels that run simultaneously.

The 16-bit ITU has five timer channels. The ITU allows for synchronizing the timers (i.e., five synchronized PWM outputs) and triggering the TPC, which can output 16-bit data (groups of 4 bits) synchronized with the ITU. In addition to the dual standard UARTs, the ’3048 contains a smart card (SC) interface. The asynchronous serial clock and data I/O format of the SC interface is similar to the asynchronous UART 8-bit format with parity. However, the receiving device can indicate a parity error (during the normal stop bit time) for an automatic retransmission of data.

The ’3048 has three power-down states for reducing power consumption. Sleep mode halts the CPU while on-chip peripherals function via the system clock. Hardware Standby mode requires a logic low on the input pin (*STBY), thereby disabling internal peripherals and placing outputs in a high-Z state. This is also accomplished through Software Standby mode by setting the SSBY bit in the SYSCR register before going to sleep.

In User mode, flash memory programming is handled under user program control by 1-, 28-, and 32-KB block erasures and 128-byte block writes.

Because this handles up to 64 KB of code and the ’3048 has 128 KB of flash memory, you cannot directly use this method to program the additional 64 KB. You must supply code that will establish a new boot format to accept data and place it anywhere in the flash memory address space (i.e., the S-record file).