Issue 133 August 2001
MSP430 News Flash:

Recognizing the Flexibility of Reprogramming

Start • MSP430F1121 • Comparatively Speaking • Battery Monitor • Dynamic Inputs • RC To The Rescue • E(OR I)IN • It's Only The Beginning • Sources & PDF

COMPARATIVELY SPEAKING
I want to narrow the focus of this article somewhat. Many applications for a micro require monitoring some kind of sensor. Because most sensors are analog (more than just a switch closure), there is an advantage to using a micro with an ADC. You may have noticed in Figure 1 that the ’F1121 doesn’t have an actual ADC. How can the comparator peripheral be used for measuring sensor input?

Figure 2 is a block diagram of the comparator and supporting circuitry available on the ’F1121. Two 8-bit registers are used to configure the comparator. CAON (CATL1.3) enables power to the comparator. This will add ~30 µA to the current requirement of the micro.

(click here to enlarge)

Figure 2—This block diagram shows the flexibility of the comparator’s configuration.

The (+) and (–) inputs to the comparator can be connected to either an external pin or an internal reference voltage. P2CA0 (CACTL2.2) connects or isolates external pin P2.3, and P2CA1 (CACTL2.3) connects or isolates external pin P2.4 to and from intermediate comparator connections. CARSEL (CACTL1.6) applies an internal voltage to one or the other of the intermediate comparator connections.

These intermediate connections are routed to the comparator inputs by CAEX (CACTL1.7). This bit connects the intermediate signals CA0 to the (+) input and CA1 to the (–) input or reverses the connections. This bit essentially swaps the inputs. In addition, the comparator’s output is inverted by CAEX. When CAEX = 0, CAOUT = 1 and the (+) input is greater than the (-) input. When CAEX = 1, CAOUT = 1 and the (–) input is greater than the (+) input. I’ll cover this in greater detail later in the article. Because the comparator’s design is that of little hysteresis, its output may swing wildly as the two inputs approach the same potential. Bit CAF (CACTL1.1) can apply a small LP filter (2-µs RC) to reduce these oscillations.

The internal reference voltage is selected via bits CAREF0 (CACTL1.4) and CAREF1 (CACTL1.5). There are four selections—none, relative 0.5 VCC, relative 0.25 VCC, and an absolute (but temperature-sensitive) voltage source of ~0.55 V.

Typically, to reduce pin count, analog inputs are multiplexed with digital inputs as alternate functions. Input circuitry for digital signals is designed to keep signals at logic levels and current to a minimum. As a result, this doesn’t work well for analog inputs. The solution is to allow the CMOS buffer circuitry to be disabled to reduce current consumption on inputs where the signal is something other than logic levels. Register CAPD contains a control bit for each port input (CAPD.0–CAPD.7). Any bit position with a “1” disables the input buffer for that input pin.

There are a couple of points worth mentioning on the comparator inputs. First, it is possible to configure the comparator with inputs left unconnected to either an input pin or reference source. This will surely give you unpredictable results. Second, it is also possible to have an internal reference voltage present at an input. This can be used as an external reference with a buffer to prevent loading.