July
2005, Issue 180
Solar-Powered
Water Pump Controller
Cypress
PSoC High Integration Challenge 2004 Contest Winner
SAMPLE
PROCESSING
The
background tasks are split between the ADC sample processing
and the periodic tasks, which are synchronized to the
voltage zero crossing. These periodic tasks run at a
variable frequency between 25 and 65 Hz. A finite state
machine slices up the periodic tasks with the ADC sample
processing to minimize jitter to the measurements.
The
ADC sample-processing algorithm triggers whenever the
ADC hardware measures a sample. It’s responsible for
controlling the analog multiplexer and cycling through
the AC and DC voltages and current channels. The DC
voltage and current measurements are filtered with integrate
and dump accumulators, which are reset after each line
cycle.
The
AC samples compute the RMS output voltage by squaring
and accumulating 16 samples per line cycle. After the
square root is taken at the end of the line cycle, the
accumulator is reset.
