July 2005, Issue 180

Solar-Powered Water Pump Controller
Cypress PSoC High Integration Challenge 2004 Contest Winner

ANALOG SIGNAL ACQUISITION

The pump inverter monitors three analog signals: the AC voltage, the DC array voltage, and a coarse representation of the DC current. The CY8C27443’s sigma-delta 8-bit ADC operates at a sampling frequency of 11,718 Hz. This uses the internal band-gap reference voltage range of ±1.3 V. The 1.3-V analog ground is provided on the P0[4] pin, thereby allowing it to be fed to external scaling circuitry to offset incoming signals. The input to the ADC is connected to a programmable gain amplifier (PGA) block configured as a voltage-follower to provide a high-impedance input. This amplifier is connected to a 4:1 multiplexer, which selects the input channel to connect to the ADC.

The AC voltage signal is taken from one of the motor’s phases and measured from line to neutral. This has the nominal value of 230 VRMS, or 325 VPEAK. A peak measurement value of 400 V provides headroom for excessive voltages. This is scaled down with a divider network to the internal reference range of ±1.3 V. An additional parallel capacitor supplies a single-pole RC filter to provide a roll-off before the ADC’s sampling frequency. An instrumentation amplifier PSoC block processes the signal coming to the IC because it isn’t referenced to supply ground and it requires a differential amplifier. The amplifier’s output is fed directly to the analog multiplexer via P0[3].

The DC array voltage input, which is referenced to supply ground, has a maximum value of 100 V. This enables you to use a simpler single-chain resistive divider. You can feed it to the multiplexer via P0[5].

The DC current is sensed with the MOSFET drain-source voltage drop when it’s turned on. The voltage drop in a MOSFET is equal to the drain-source current multiplied by the RDS(ON) resistance, so you can infer the DC current from this measurement. The maximum value of the three H-Bridge currents is selected using a series of parallel diodes connected in an OR arrangement. A switched-capacitor, second-order, low-pass filter PSoC block filters the current signal to attenuate the switching frequency components. This signal contains harmonics of the switching frequency, which are attenuated via a Butterworth filter with its 3-dB frequency set to 5 kHz. This frequency also conveniently allowed the ADC clock to be reused to operate the filter block. The signal output from the filter on P0[2] is fed back as an input on the ADC multiplexer via P0[7].