June 2000, Issue 107

Low-Cost Software
Bell-202 Modem

MCU ARCHITECTURE

For an 8-bit MCU to do what the 16- and 32-bit MCUs do, it needs many of the same architectural features, including a streamlined, four-stage RISC-like pipelined architecture to minimize code size and maximize performance.

Coupled with extremely fast on-chip instruction and data memory, this arrangement permits every instruction to be executed in a single clock cycle. A 50-MHz clock can provide an instruction throughput rate of 50 MIPS, and a 100-MHz clock gives 100 MIPS.

Another requirement is a deterministic interrupt-response capability that services interrupts in a small and precise number of cycles every time. With older architectures, tasks are only interrupted at instruction boundaries, so the number of cycles required to respond to an interrupt is unpredictable.

This setup not only produces slow interrupt responses but also introduces jitter into the system timing, which limits performance and accuracy. Short predictable interrupt-response times, with critical registers automatically stored in special hardware stacks during an interrupt, eliminate the problem of jitter and ensure proper execution of virtual peripheral functions.