Issue
155 June 2003
Encore!
Zilog's
Z8 Flash Memory-Based Micro
DEBUGGER
The
integrated on-chip debugger (OCD) is rapidly becoming
a standard function in micros. The Z8 Encore!’s OCD
provides access to the register file, program, and data
memory. Advanced features include the setting of breakpoints
and watchpoints, and the immediate execution of eZ8
CPU instructions.
The
OCD consists of four primary functional blocks: transmitter,
receiver, auto data rate generator, and debug controller.
Figure 4 illustrates the architecture of the OCD using
the DBG pin for communication with an external host.
This one-pin interface is a bidirectional open-drain
interface that transmits and receives data (not simultaneously).
The serial data on the DBG pin is sent using the standard
asynchronous data format defined in RS-232. This pin
can act as an interface from the Z8 Encore! to the serial
port of a host PC using minimal external hardware. Figure
5 shows a typical circuit that’s necessary to connect
the DBG pin to a PC. (This circuit is Zilog’s target
interface module board.)
|
(Click
here to enlarge)
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Figure
4—A half-duplex serial channel is created via the
Z8 Encore! DBG pin. This single pin gives you access
to the CPU via the debug controller. |
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(Click
here to enlarge)
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Figure
5—A 2 × 3 square pin connector supplies power, ground,
and a single communication line (DBG) from the target
PCB to this simple half-duplex serial adapter. The
MAX232 converts serial from a host PC to the 3.3-V
logic levels used by the DBG interface pin. |
If
the DBG pin is low when the Z8 Encore! exits Reset mode,
the OCD automatically puts the Z8 Encore! into Debug
mode. To run over a range of data rates with various
system clock frequencies, the OCD has an auto data rate
detector/generator. After a reset, the OCD is idle until
it receives data. The OCD requires that the first character
sent from the host is the character 80H. The character
80H has eight continuous low bits (i.e., one start bit
and seven data bits). The auto data rate detector measures
this period and sets the OCD data rate generator accordingly.
The system clock clocks the auto data rate detector/generator.
The minimum data rate is the system clock frequency
divided by 512; the maximum recommended data rate is
the system clock frequency divided by eight. After the
data rate is set, you can communicate directly with
the OCD.
The
BRK instruction (opcode 00H) signals the OCD. If breakpoints
are enabled, the OCD enters Debug mode and idles the
eZ8 CPU. If breakpoints are disabled, the OCD ignores
the BRK signal, and the BRK instruction operates as
an NOP.
A
breakpoint is established by writing 00H to the desired
address and overwriting the current instruction. To
remove a breakpoint, the corresponding page of flash
memory must be erased and reprogrammed with the original
data.
If
you aren’t looking to take control of the OCD with a
roll-your-own debugging application, then Zilog’s Z8
Encore! test-drive kit, complete with its great integrated
development environment (IDE), is all you need. Again,
refer to Fred’s aforementioned column to learn more
about the details.
