Issue 155 June 2003
Encore!
Zilog's Z8 Flash Memory-Based Micro

DMA

Earlier, I briefly mentioned the direct memory access (DMA). I’ll go into more detail now. The DMA controller provides two additional independent DMA channels. These channels—DMA0 and DMA1—transfer data between the on-chip peripherals and the RAM or from the RAM to the on-chip peripheral control registers.

Either DMA controller can be initiated from any of the timers, the UARTs, or the I2C interface. Both byte and word transfers can be handled. Loading the start and end address registers (pointers to RAM) allows multiple transfers to automatically take place (e.g., a serial receive or transmit buffer).

 INTERRUPTS

The interrupt controller on the Z8 Encore! prioritizes the interrupt requests from the on-chip peripherals and GPIO port pins. Twenty-four unique interrupt vectors offer plenty of control over enabled interrupt sources via through levels of individual programmable priority. GPIOs have eight selectable rising- and falling-edge interrupts (i.e., four dual-edge interrupts). The CPU supports both vectored and polled interrupt handling. For polled interrupts, the interrupt controller doesn’t affect operation. Table 1 shows interrupt vector addresses and priority ranking within the same interrupt level.

Interrupt priority is set with 2 bits for each interrupt enable. Essentially, a 00 disables the interrupt; a 01, 10, or 11 enables the interrupt and sets the priority low to high (respectively). Continuous assertion interrupts are those that aren’t cleared by the CPU upon acknowledgement. Note that these are mostly the communication peripherals. The interrupts must be cleared as part of the interrupt routine.

RESET

The Z8 Encore! contains a reset controller for Reset and Stop mode recovery operation. In typical operation, the following events cause a reset to occur: power-on reset (POR), voltage brownout (VBO), watchdog timer timeout (when configured to initiate a reset), and an external reset pin assertion. In Stop mode, a Stop mode recovery is initiated either by the watchdog timer timeout or GPIO port input pin transition on an enabled Stop mode recovery source.

Executing the eZ8 CPU’s Stop instruction places the Z8 Encore! in Stop mode, during which the primary crystal oscillator and system clock are disabled, and the CPU is idle. In addition, the program counter (PC) stops incrementing, the watchdog timer’s internal RC oscillator continues to operate (if enabled, the watchdog timer continues to operate), and all of the other on-chip peripherals are idle.

To minimize current in Stop mode, all GPIO pins that are configured as digital inputs must be driven to one of the supply rails (e.g., VCC or GND). The Z8 Encore! is brought out of Stop mode using the Stop mode recovery.

The watchdog timer is a 24-bit counter based on an internal RC oscillator. The minimum count overflow is ~60 µs, and a maximum count overflow is over 5 min.! The overflow can cause a reset or wakeup.