Issue
155 June 2003
Encore!
Zilog's
Z8 Flash Memory-Based Micro
DATA
SPACE
Data
space is 128 bytes of read-only memory at the top of
the eZ8 CPU’s 64-KB data-memory address space. This
ROM space contains a 20-character ASCII alphanumeric
part number beginning at address FFC0H. (It’s left-justified
and padded with zeros.)
GPIO
Four
registers for each port provide access to GPIO control,
input data, and output data. Table
2 shows lists these registers.
The
port address and control registers provide access to
subregisters for port configuration and control. Subregisters
control the data direction, alternate function, output
control (open-drain), high drive enable, and Stop mode
recovery source enable for each pin of the port.
The
subregister of choice is selected by writing to the
Port Address register. The value for the subregister
is written to the subregister by writing it to the Port
Control register. The indirect addressing of subregisters
helps prevent unauthorized configuration alterations.
ANALOG
Zilog
uses the typical three major functional blocks (i.e.,
converter, analog multiplexer, and voltage reference
generator) for the ADC. The ADC converts an analog input
signal to a 10-bit digital representation of the input
signal. The input analog multiplexer selects one multipurpose
input as the conversion source. The reference voltage
for the conversion may come from the external VREF pin,
or the voltage reference generator generates it internally.
If
the ADC is idle (i.e., no conversions in progress) for
160 consecutive system clock cycles, portions of the
ADC are automatically powered down. From this power-down
state, the ADC requires 40 system clock cycles to power
up. The ADC automatically powers up when a conversion
is requested using the ADC Control register.
The
ADC can be configured for either single or continuous
conversions. A single-shot conversion instructs the
ADC to perform a single analog-to-digital conversion
on the selected analog input channel. After completion
of the conversion, the ADC shuts down. Continuous conversion
allows the ADC to continuously perform analog-to-digital
conversions on the selected analog input. Each new data
value overwrites the previous value stored in the ADC
Data registers. An interrupt is generated only at the
end of the first conversion after enabling.
The
direct memory access (DMA) controller controls the operation
of the ADC, including analog input selection and conversion
enable. You can pick the number of channels to be sampled
and where the conversion values are to start in RAM.
The ADC_DMA controls the channel selection, conversion,
and conversion data storage for each channel in the
sequence. This can be a single pass through all selected
channels or continuous conversions.
TIMERS
All
timers are identical 16-bit up-counter/timers. Each
timer has a control register with a 3-bit prescaler
value that can be set to divide by 1, 2, 4, 8, 16, 32,
64, or 128. This register also sets the operational
mode. One-shot, Continuous, Counter, PWM, Capture, Compare,
Gated, and Capture/Compare modes are available. Gate/capture
input and clock outputs for each timer complete the
flexible timer/counter structure illustrated in Figure
2.
|
(Click
here to enlarge)
|
Figure
2—All Z8 Encore! family products have at least three
16-bit timer/ counters (with prescaler). Each provides
an asynchronous PWM output. |
