Issue
130 May 2001
DDS-GEN—Part
2: The Generator
Start •Direct Digital Synthesis?
• The AD9852 monster chip •Hardware
• Prototype Construction •On The Software Side •Design Methodology •What’s Next? •Sources & PDF
Hardware
This project
tries to use as many DDS chip features as possible. Apart
from the power supply, there are six main subsystems (see
Figure 3). The AD9852 DDS generator and system clock are
one subsystem. The second subsystem is its output filters
and the high-frequency output amplifier/offset generator.
Then, there’s the Philips 87LPC764 serving as the
main microcontroller. And, the I2C-driven user interface
(described in Part 1, Circuit Cellar 129). The next subsystem
is the A/D system that manages the AM/FM/PM analog modulation
input (generated in software). And, the last subsystem
is the expansion connectors for future plug-ins.
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(Click
here to enlarge)
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Figure
3—The main microcontroller communicates with
the I2C-MMI subsystem via an I2C bus, and communicates
with the DDS chip and modulation ADC via an SPI bus. |
The power supply
is not the simplest part of this design (see
Figure 4 [download the PDF
to view clearly]) because of EMC/EMI constraints and
mixed 5-/3-V design. To minimize noise on the analog output,
separate supplies are used for the 5-V digital microcontroller,
±5-V analog output amplifier, 3.3-V digital DDS chip and
buffers, and 3.3-V analog DDS chip.
Standard 78L05/79L05
regulators are used for the ±5-V outputs, and a reliable
L200 (U3) is used for the 3.3-V outputs. Filtering coils
are inserted in all power lines to minimize 300-MHz cross-talk
and separated analog/digital grounds are implemented.
The DDS-GEN
main system clock is 20 MHz, derived from a standard 40-MHz
canned oscillator and divided by 2 by U5A to improve jitter
performance (see Figure 5 [download
the PDF to view clearly]). Its modest stability (100
ppm) is enough for most applications. However, the oscillator
is mounted on a plug-in PCB and can be replaced easily
by a high-performance, 40-MHz OVCXO, which would boost
the stability to 3 ppm (for a price hike). The 20-MHz
clock is multiplied by 15 thanks to the PLL integrated
in the DDS chip, giving a 300-MHz system clock.
The AD9852 is
serially controlled by the microcontroller with an SPI-compatible
interface through a 5-to-3.3-V level converter. The I/O
update signal is used as an interrupt source to the microcontroller.
This enables you to synchronize the firmware with the
DDS chip operation. The pulse is captured by a fast JK
register (74ACT109), because it’s only eight clock
pulses long at 300 MHz. And, it has a 300-MHz internal
clock frequency that enables you to synchronize the microcontroller
with the DDS chip.
The TTL I/O
signals (Keying, Square Output, FSK/PSK, and so on) are
buffered and shifted to standard TTL levels by Philips’
74LVT245 (U6). These 3.3-V transceivers have 5-V, TTL-compatible
I/O signals and an impressive 2.4-ns propagation delay.
Last but not least, a small TL7705ACP provides a clean
reset pulse to the DDS chip and microcontroller.
The main microcontroller
is an 87LPC764, interfaced to the DDS chip through 5-to-3.3-V
converters. For more information, check out the datasheet.
[2] The microcontroller is clocked from the main 20-MHz
system clock. Its I2C port is used to control the user
interface and plug-in boards. The UART is configured as
an SPI controller, and drives the DDS, external A/D converter,
and plug-in boards with distinct chip selects.
The last part
of the design is the analog stuff (see Figure
6 [download the PDF to view
clearly]), which is the difficult part for firmware-oriented
types. To work with frequencies above 100 MHz you need
experience.
First of all,
each complementary output of the main DAC is fed through
a passive 120-MHz elliptic filter to get out of the band
frequencies. I borrowed the filter design from Analog
Devices. [1] I modified the coil values to be integer
multiples of a single value (just try to buy eight different
SMD coil values in small quantities and you’ll understand
why I did it that way). I checked the frequency response,
which still looked good (see Photo 1). The two complementary
and filtered sine waves go back to the AD9852’s internal
high-speed comparator to generate the square output.
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(Click
here to enlarge)
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Photo
1—A simulation of the transfer function of the
150-MHz low-pass filter shows a 70-dB rejection above
cutoff frequency. This simulation was done using SpiceAge
software. |
For the analog
output, a pair of high-frequency relays selects either
the sinus output (one of the two filtered signals from
the AD9852 DACs) or the output of one of the plug-ins’
slots. The selected signal is amplified and DC is offset
by an AD8002 high-speed current amplifier.
This amplifier
has a gain bandwidth of 600 MHz at –3 dB and provides
0.1-dB flatness from 0 to 60 MHz. That isn’t perfect
for this application, but it’s a good performance
versus price trade-off. Moreover, the 1200-V/µs slew rate
makes it adequate for your pulse generator applications.
Last, the external
modulation input (used for AM/FM/PM modes) is first scaled
and DC offset by a standard LM324 (U14) in order to give
a 0- to 5-V signal from the ±5-V input. This signal is
then fed into a small TI TLV1572. This 10-bit A/D converter
is serially connected to the microcontroller through the
shared SPI bus.
© Circuit Cellar,
The Magazine for Computer Applications. Reprinted with
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