Issue
130 May 2001
DDS-GEN—Part
2: The Generator
Start
•Direct Digital
Synthesis? • The
AD9852 monster chip •Hardware
• Prototype Construction
•On The Software Side
•Design Methodology
•What’s Next?
•Sources & PDF
The
AD9852 monster chip
It’s possible
to design a DDS generator with discrete components or
an FPGA, or even with a full-software implementation on
a microcontroller for low-speed applications. However,
some manufacturers have pretty impressive dedicated DDS
chips.
I chose the
AD9852 for this project (see Figure 2). [1] This 80-pin
LQFP chip integrates anything needed to build a high-performance,
DDS-based sinus generator. And, the AD9852 can be driven
by a high-speed parallel bus or SPI-compatible serial
port.
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(Click
here to enlarge)
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Figure 2—The
DDS is in the upper left section, clocked by an integrated
PLL clock multiplier. Its output is filtered by a
digital inverse sin(x)/x filter before going through
a digital multiplier for amplitude modulation and
ramping. The AD9852 also contains a complex frequency/phase
tuning logic, two 12-bit DACs, and a high-speed comparator.
[1] |
Need speed?
The AD9852ASQ has a 300-MHz maximum clock frequency that
can be internally generated thanks to an on-chip clock
multiplier. The output frequency is limited only by Nyquist
(150 MHz) and the slope of the external low-pass filter.
A lower grade version, the AD9852AST, is limited to a
reasonable 200 MHz.
The phase registers
are 48-bits long, giving a microhertz resolution for signals
up to the maximum frequency. This chip also integrates
a pair of 12-bit DACs (one is genera-purpose) as well
as a high-speed comparator to generate low-jitter square
signals.
Around the DDS
generator, the AD9852 offers a full set of logic blocks
to support the following modulation modes: amplitude (AM),
frequency and phase (FM/PM), shaped on/off keying, ramped
frequency shift (FSK), and phase shift keying (PSK).
In AM mode,
a 12-bit multiplier can be inserted prior to the DAC.
And, the multiplier value can be modified on the fly via
the serial or parallel port (up to 100-MHz update frequency),
giving fully digital control of the output signal amplitude.
The phase increment and phase offset registers can be
updated on the fly, providing an easy way to implement
frequency or phase modulation.
In the Shaped
On/Off Keying modes, the signal amplitude is automatically
switched from 0 and 100% depending on the logic level
applied on a dedicated pin. An integrated ramp counter
enables a smooth transition with a programmed linear amplitude
slope.
In FSK mode,
two phase increment registers can be alternately selected
using an external pin. The output signals switch between
the two preselected frequencies. Another integrated ramp
counter allows you to automatically ramp the frequency
between the two setpoints in a linear fashion in order
to reduce unwanted harmonics.
And, with the
PSK mode, you can directly select a pair of 14-bit phase
offset registers with a pin signal, thus immediately shifting
the output signal phase between the values.
I’ve described
only the modes I used in my DDS-GEN project. Feel free
to take a look at Analog Devices’ documentation to
discover the other myriad of options for this chip. [1]
I caution you, the AD9852 is powerful yet power-hungry.
It is a 3.3-V chip but eats up to 900 mA at maximum frequency
if all blocks are switched on.
The AD9852ASQ
is packaged in a thermally-enhanced LQFP body, but it
needs a four-layer PCB and industrial-range soldering
tools to be used safely. On my prototype, I adapted a
large TO3-type heatsink fitted directly on the chip with
small springs. It isn’t beautiful, but it works perfectly.
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