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May 2000, Issue 118

Building a RISC System In AN FPGA Part 3:
System-on-a-Chip Design


by Jan Gray

Now that the xr16 RISC processor is complete, it’s time to tie everything together and wrap up this series. In this final part, Jan designs a demo system that includes an on-chip bus, memory controller, video controller, and peripherals.


Start XS40 Board A System-On-A-ChipDecisions,Decisions Bus Controls Bus Interface External I/O Interface? MEMCTRL Design Paralell Port I/OVideo Controller System Bring-UpSeries Wrap-Up Software and PDF

The xr16 RISC processor is designed, now it’s time to design the rest of the System-on-a-Chip (SoC). Besides the CPU, the FPGA hosts an on-chip bus, bus controller, parallel port, RAM, video controller, and an external SRAM controller.

This month, I’ll show how simple interfaces can make SoC design as straightforward as classic CPU, glue logic, memory, peripherals, and PCB design used to be.

2005034 photo 1.jpg (52447 bytes)

Photo 1—Here’s the xs40 board, with the project design loaded into the FPGA
and running a demo program that’s drawing graphics on the monitor.