EXTERNAL I/O INTERFACE?

There isn’t one. If it were necessary to attach external peripherals, perhaps to the XD7:0 bus, you might design some on-chip external peripheral adapter macros. Just like an on-chip peripheral, each adapter would take CTRL and some SELi, but its job would be to use additional I/O pins to control its peripheral IC’s chip selects and so forth. Of course, as a CTRL15:0 client, it would be able to raise interrupts, insert wait states, and so forth.

EXTERNAL RAM

The external RAM is a classic 32-KB fast asynchronous SRAM with a 15-ns access time (tAA). Its pins include A14:0 (address), D7:0 (data in/out), /CS (chip select), /WE (write enable), and /OE (output enable).

Refer to Figure 2 and the external bus and SRAM interface block of Figure 5.

XA14:1 is 14 IOBs configured as OFDXs (output flip-flops with clock enables). XA14:1 captures the next address AN14:1 at the start of each new memory transaction. XA0 (XA_0) is the least significant bit of the external address. It is a logic output and can change on either CLK edge.

XD7:0 is eight IOBs configured as eight sets of simultaneous OBUFTs (tri-state output buffers), IBUFs (input buffers), and IFDs (input flip-flops).

During a RAM write, XDOUTT is asserted, RAMNOE is deasserted, and the OBUFTs drive D7:0 out onto XD7:0.

During a RAM read, XDOUTT is deasserted, RAMNOE is asserted, and the RAM drives its output data onto XD7:0. The data is input through the IBUFs and latched in the XDIN IFDs (on each falling CLK edge).

To keep the CPU busy with fresh new instructions, the system reads both bytes of a 16-bit word in one cycle. In the first half cycle, it sets XA0=0, reading the MSB, and latches it in XDIN. In the second half cycle, the system sets XA0=1, reading the LSB, and reads it through IBUFs. The catenation of these two bytes, XDIN15:0, feeds the CPU’s INSN port, the video controller’s PIX port, and D15:0 via the byte-wide tri-state buffers LXD and UXD.

Writes to asynchronous SRAM require careful design. Let’s see if we can safely write one byte per clock cycle. The key constraints are:

• address must be valid before asserting /WE
• data must be valid before deasserting /WE
• /WE must be deasserted briefly
• no adddress/data hold time after /WE

I required a fully synchronous design to be able to slow or stop the clock and was unwilling to employ any asynchronous delay tricks.

Accomplishing this requires one half clock to settle the write address, one half clock to assert /WE, and one half clock to deassert it. Therefore, byte writes take two full cycles, and word writes take three (e.g., a word write takes six half cycles W1–W6):

• W1: assert XA14:1, data LSB, XA0=1
• W2: assert /WE
• W3: deassert /WE, hold XA and data
• W4: assert data MSB, XA1=0
• W5: assert /WE
• W6: deassert /WE, hold XA and data