BUS
CONTROLS
MEMCTRL, the system bus/memory controller, interfaces
the processor to the on-chip and off-chip peripherals.
It receives the pipelined "next transaction"
memory request signals AN15:0, WORDN, READN, DBUSN,
and ACE from the CPU. Then, it decodes the address,
enables some peripheral or memory, and later asserts
RDY in the clock cycle in which the memory cycle completes.
I/O registers are memory mapped (see Table 1).
| Address
0000-7FFF
0000
0010
FF00-FFFF
FF00-FF1F
FF21
FF41
FF60-FF7F
… …
FFE0-FFFF
|
Resource
external 32-KB
RAM, video frame buffer
reset handler
interrupt handler
I/O control registers, 8 peripherals × 32
bytes
0: 16-word on-chip IRAM
1: parallel port input byte
2: parallel port output byte
3: unused
… …
7: unused
|
Table 1—The system
memory map includes eight decoded
peripheral control register address blocks. |
There
are eight transaction types: (external RAM or I/O)
´ (read or write) ´ (byte or word), all decoded from
AN15:0, WORDN, and READN.
MEMCTRL
manages transfers on the on-chip data bus D15:0 and
the external data bus XD7:0 by asserting various tri-state
output enables (xT) and control register clock
enables (xCE). These enable signals are asserted
according to the transaction type (see Table 3).
| Enable
LDT
UDT
UDLDT
XDOUTT
LXDT
UXDT
p/LDT
p/UDT
p/LCE
p/UCE
|
Effect
D7:0 ¬ DOUT7:0
D15:8 ¬ DOUT15:8
D7:0 ¬ DOUT15:8
XD7:0 ¬ D7:0
D7:0 ¬ XDIN7:0
D15:8 ¬ XDIN15:8
D7:0 ¬ p/D7:0
D15:8 ¬ p/D15:8
p/D7:0
:= D7:0
p/D15:8
:= D15:8
|
| Table 2—There are
a set of enables p/* within each peripheral.
DOUT15:0 is the CPU store data output register
(see Part 1, Circuit Cellar 116). |
For
example, during sw r0, 0xFF00, MEMCTRL decodes
an I/O write word request. It asserts LDT and UDT,
driving the store data onto D15:0, and asserts IRAM/LCE
and IRAM/UCE, writing D15:0 into IRAM’s SRAMs:
IRAM/D15:0 := D15:0 ¬ DOUT15:0
| Transaction
RAM read byte
RAM read word
RAM write byte
RAM write word
I/O read byte
I/O read word
1+
I/O write byte
1+
I/O write word
1+
|
Cycles
1
1
2
3
1+
1+
1+
1+
|
Enables
LXDT
LXDT, UXDT
LDT, XDOUTT
LDT or UDLDT,
XDOUTT
p/LDT
p/LDT,
p/UDT
LDT, p/LCE
LDT, UDT p/LCE,
p/UCE
|
Table 3—Depending
on the memory transaction, different bus
output enables and register clock enables
are asserted |
Next,
consider a store to external RAM: sw r0,0x0100.
Because the external data bus is only eight bits wide,
first store the least significant byte, then the most
significant byte. First, MEMCTRL asserts LDT and XDOUTT:
XD7:0 ¬ D7:0 ¬ DOUT7:0
Later,
it asserts UDLDT and XDOUTT:
XD7:0 ¬ D7:0 ¬ DOUT15:8
