DECISIONS, DECISIONS

Before examining the design, let’s briefly explore the on-chip bus design space. (This is not the sort of thing you worry about when designing to someone else’s microprocessor, but in an FPGA SoC, you have a little more freedom.)

Bus design issues include how many bus masters are permitted, how is the bus clocked and pipelined, how wide is it, does it provide byte addressing, and is it split or unified with the processor core RESULT bus.

For XSOC, the pipelined on-chip 16-bit data bus D15:0 is single-mastered (but recall the CPU also performs DMA transfers), the bus clock is the CPU clock, and the on-chip data bus is unified with the processor’s RESULT15:0 data bus. All of these design decisions help to keep this project simple.