A
SYSTEM-ON-A-CHIP
I’ll build an integrated system from the resources
at hand—the FPGA, RAM, the video and parallel
ports, and the 12-MHz oscillator.
I
used the RAM for program, data, and video memory.
The byte-wide, asynchronous SRAM isn’t ideal,
but it is fast enough for you to read and latch a
byte on each clock edge, thereby fetching a 16-bit
instruction during each cycle.
By
displaying all 32 KB of RAM, you can fashion a bitmapped
576 ´ 455 monochrome video display at VGA-compatible
sync frequencies. How quaint, to watch every bit on
screen!
Refer
also to Figure 4, the FPGA top-level schematic. It
includes the processor (P), the system memory/bus
controller (MEMCTRL), the on-chip 16-bit data bus
(D15:0), on-chip peripherals (PARIN, PAROUT, and IRAM),
the external SRAM interface, and the VGA video controller.
| Figure 4—The
processor (P) issues requests to MEMCTRL,
accessing instruction and data via the on-chip
bus D15:0 or external SRAM. Integrated peripherals
provide parallel port I/O and on-chip RAM.
The VGA controller fetches pixel data via
DMA. |
