SERIES WRAP-UP

In this three-part series, I have presented the complete design and implementation of a real, full-featured, pipelined microprocessor and an integrated System-on-a-Chip. I designed a new instruction set, ported a C compiler, and discussed how to build practical CPUs in inexpensive FPGAs. I also explored pipelined processor design.

In this article, you have seen how to build an integrated system with reusable cores. The Circuit Cellar web site provides the full set of schematics, tools, links, and such necessary for you to download and build this project, with the help of the Student Edition tools and the XESS XS40-005XL proto board. Have fun!

Ashok Patel inspired these articles long ago when he and his friends kindly taught a teenager digital design. Later, he challenged me to share in kind what I have learned.

Jan Gray is a software developer whose products include a leading C++ compiler. He has been building FPGA processors and systems since 1994, and he now designs for Gray Research LLC. You may reach him at jan@fpgacpu.org. 

Please note that I do not warrant that you have the right to build something based upon the ideas discussed in this series of articles under the relevent intellectual property laws in your jurisdiction.