circuitcellar.com
Magazine Support   Digital Library   Products & Services   Suppliers Directory 
 
 





 

Issue 153 April 2003
E-Chips


THE 80 WAY       

These days, you don’t necessarily need a 32-bit chip to get on the I-way. A lot of interesting applications have low data rate requirements and don’t necessarily need every protocol in the alphabet soup.

New chips from Zilog and Rabbit make the point. Although only eight bits in spirit (i.e., actually 24- and 16-bit ALUs, respectively), they demonstrate that although less may not be more, it may be enough to get the job done.

In my original article covering the then new eZ80 (Circuit Cellar 139), I proposed that it would be a good idea for Zilog to add built-in flash memory and an Ethernet MAC. Enter the eZ80F91. Starting with a 50-MHz version of the CPU core, the ’F91 adds 256 KB of flash memory to the original’s 8 KB of high-speed SRAM. In addition, the 10/100 Ethernet MAC gets its own 8 KB of packet RAM to play with.

As an aside, note that Zilog is also introducing other versions (e.g., ’F92 and ’F93) without the Ethernet that have less memory and cut the clock rate to 20 MHz. Prices range from about $8 to $16 (10,000 quantity), accordingly.

Peripherals include the usual suspects: four timers, two UARTs, SPI, I2C, a watchdog timer, etc. I noticed that the UARTs have a specific built-in IRDA capability. With all the buzz around wireless networking, I wonder if infrared shouldn’t get a little more attention. Admittedly, the IRDA story has been complicated over the years by some fits and starts in terms of protocol complexity and feature creep; however, the recent widespread use of IR in PDAs should encourage designers to take another look.

As I write this column, Zilog is running a $399 special on the ’F91 development kit. That’s a good deal considering the package includes everything: an evaluation board, C compiler, emulator, and TCP/IP stack (see Photo 2).

(Click here to enlarge)

Photo 2—Batteries may not be included, but everything else is in the Zilog eZ80F91 evaluation kit.

As for Rabbit, it’s no surprise their upcoming R4000 makes an Ethernet play. Rabbit and its sister company Z-World have been leaders in bringing networking to blue-collar embedded apps. Currently, I don’t have a full spec for this third-generation follow-on to the R2000 and R3000, but let me talk about what I know so far (see Figure 2).

(Click here to enlarge)

Figure 2—The earlier Rabbit 2000 and 3000 chips have been making network connections for a long time, so it’s no surprise to find on-board Ethernet in the new Rabbit 4000.

Considering the subject at hand, the built-in Ethernet deserves the first look. Here, Rabbit takes a bit of a different tack than most others by eschewing a full 10/100 MII interface in favor of a leaner-and-meaner 10BaseT full-duplex-only setup.

Some of you will question the compromise, but I’m giving Rabbit the benefit of the doubt based on their historic experience in (and my own take on) the embedded network marketplace. Simply put, the Rabbit 4000 is more about cost than bit-blasting bragging rights, and their decision cuts the fat in a number of ways.

First, an official 10/100 MII interface calls for 18 pins to an external transceiver (PHY) chip. In contrast, Rabbit claims the ’4000 will direct connect to the Ethernet with a mere $1 of external parts. Furthermore, making an honest effort to support the higher 100-Mbps data rate (not to mention 200-Mbps full duplex) demands a lot of dedicated hardware (i.e., the specialized DMA, buffer managers, packet RAM, etc. found on the other E-Chips). On the contrary, the ’4000 can handle 10 Mbps in an entirely conventional manner with cycle-stealing DMA to and from main memory.

Ditching half duplex also simplifies the silicon, because you can say bye-bye to all of the baroque trinkets (e.g., collisions, back-off, retries, etc.) associated with CSMA/CD. In Rabbit’s view, it’s better to apply that silicon to the bottlenecks that real-world applications are likely to encounter. For instance, the ’4000 includes a dedicated public key encryption calculation engine that cuts the time for serving a secure web page by a factor of 10 (from 20 to 2 s).