Issue
141 March 2002
You
Too Can Design with SoC
A
Design Challenge 2002 Primer
byJeff
Bachiochi
Analog
Getting any
kind of analog support in a microcontroller is a relatively
new idea. Cypress incorporates 12 analog PSoC blocks in
CY8C2xxx devices. These analog blocks are continuous-time
and switch-capacitive. The four continuous-time blocks
contain programmable gain/attenuation circuitry for op-amp
and comparator configuration. Three registers are used
to configure the continuous-time blocks (ACAxxCR0–2).
The first register
sets the programmable resistor divider and how it is internally
connected to provide either gain or attenuation around
the op-amp. The second register routes various signal
inputs to the inverting and noninverting inputs of the
op-amp and enables or disables output to the analog output
bus or comparator bus. The third and final register determines
if the control latch is transparent and on which phase
the latch occurs. The compensation for the op-amp also
can be enabled or disabled, which will improve the amplifier
(comparator) switching times.
The eight switch-capacitive
blocks are divided into four type A and four type B blocks.
Type A blocks have three (two switched and one non-switched)
input arrays of binary-weighted capacitors (plus a direct
capacitor input normally used in conjunction with a type
B block for bi-quad filter configurations) with a non-switched
feedback capacitor. Type B blocks have two switched input
arrays of binary-weighted capacitors, a non-switched feedback
capacitor, and an output array of binary-weighted capacitors
for bi-quad configurations.
The three control
registers associated with the two switch capacitor blocks
are similar and for the sake of brevity I will treat them
as identical. The first register (ASA/BxxCR0) defines
the first switched input capacitor value and feedback
capacitor value. This register also controls the phasing
of the capacitor switches. The second register (ASA/BxxCR1)
defines the second switched input capacitor value and
the input multiplexer selection.
The third control
register (ASA/BxxCR2) defines the third non-switched capacitor
value. This serves as the third array input for type A
blocks. For type B blocks, this is an array on the output.
ASA/BxxCR2 also controls connection to the analog and
comparator output buses and the gated switches, which
can be used to short input capacitors to ground.
There are a
few odd registers that are necessary for control and status
of the analog blocks. The analog comparator control register
(CMP_CR) allows the state of the comparator bus for each
analog column x (0–3). It also defines whether the Acolumnx
interrupt inputs are directly from the bus or qualified
with the falling edge of phase two for synchronization
purposes.
The analog synchronization
control register (ASY_CR) supports a way to perform synchronization
with the switch capacitor blocks. The SYNCEN bit will
prevent any write to the switch capacitor registers from
being operated on until the rising edge of phase one.
Also, when the block is used as a successive approximation
ADC, this register can limit the number of bits converted
to speed up conversion times.
To route analog
signals, there are two registers, an input multiplexer
(called AMX_IN) and an output buffer (called ABF_CR) register.
The input multiplexer determines which pins of port A
are used as inputs to the analog PSoC blocks. The output
buffer register enable/disables analog column x to its
port A output pin. There is also control over the strength
of the output drive.
ARF_CR, the
analog bias and reference register, controls the amount
of bias and reference used for the analog array. It also
controls power to all the analog blocks and can be used
to reduce power consumption by shutting down all of the
analog circuitry. The final register is the modulation
control register (AMD_CR). AMD_CR can select a modulation
source for analog columns zero and two by applying the
modulation source the switched capacitor block.
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(Click
here to enlarge)
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Figure
5—Analog and digital blocks can be connected via various
buses within the PSoC device. Interconnection possibilities
have been included for only the most logical paths
to decrease complexity. |
As far as the
possible interconnects go, it would be a waste of space
to allow entire flexibility, in other words to allow every
possible connection between blocks. The choices are simplified
by predetermining which make the most sense. Figures 5
and 6 illustrate the block interconnections.
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(Click
here to enlarge)
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Figure
6—The I/O pin connections have many possible paths
to the various analog and digital blocks. |
