Issue 141 March 2002
You Too Can Design with SoC

A Design Challenge 2002 Primer

Digital blocks

The eight PSoC digital blocks are divided into two types—four are basic and four are communications-type digital blocks. The communications blocks are identical to the basic blocks except for additional communications features. Each of the digital blocks (00 through 07) has a function, input, and output register.

The function register (DBAxxFN) allows the block to be defined as a timer, counter, cyclical redundancy checker, psuedo-random sequencer, dead-band generator, UART, or SPI module. Some of these functions are capable of being chained for larger than 8-bit operations. The input register (DBAxxIN) defines the path of any data or clock source used by the block. These can come from the system clocks, analog comparator bus, global input and output bus (port pins), or output from one of the other digital blocks. The output register (DBAxxOU) defines the path for any data out of the block. Here the choices are the global input and output buses or the interrupt controller. Digital block outputs also can be used as a clock input source to the analog PSoC blocks.

In addition, each of the digital function blocks has three data registers and a control/status register. The three data registers (DBAxxDR0–2) have different uses depending on the function chosen in the function register. Table 2 lists the register definitions. The control/ status register (DBAxxCR0) uses only 1 bit for enabling and disabling unless it is configured for one of the two communications functions, UART, or SPI. These functions have additional control/status bits specific to their functions.

The timer function of the digital PSoC block can capture incoming edges and interrupts on an 8-bit compare or be chained into longer counts. The timer can also create periodic interrupts. As a counter function, the block can count tics between edge inputs or, with the addition of a down counter, produce duty-cycle-adjustable PWM output.

The dead-band generator produces complementary outputs equal to the input frequency of the input, but with a programmable dead-band time (time when both outputs are off) meant to drive MOSFETs for motor control. Programmable linear feedback shift registers can be used for psuedo-random generator and cyclical redundancy check functions.

UART transmit and receive functions are treated separately. This allows you to conserve resources when bidirectional communications is not necessary. As an SPI master, clock and bidirectional data lines are implemented. If necessary, SS must be implemented using direct port pin control. In SPI slave mode, SCLK, SDAT, and SS are all implemented. Communication interrupts are generated for Transmitter Empty and Receiver Full UART functions and an SPI Transmitter Empty function.