Issue 141 March 2002
You Too Can Design with SoC

A Design Challenge 2002 Primer

Clocking

The main internal oscillator is sensitive to voltage because a crystal doesn’t control it (unless you add an external crystal). The main oscillator is factory-trimmed (8 bits) for 5 VDC. This value is stored in the trim register and can be modified if a VCC other than 5 VDC is used. An additional low-speed oscillator has a similar factory-set, 6-bit trim register. Bit 7 of the low-speed trim register allows the low-speed oscillator to be turned off. If a 32-kHz crystal is connected as an external source for the low-speed oscillator, the crystal also can serve as a phase locked loop (PLL) reference for the main oscillator, thus improving the ±2.5% accuracy of the internally trimmed oscillator.

As a base of operations, all available clocks are derived from one of these two sources (see Figure 4). So, it makes sense that these two clocks are available from the start. The SLP clock is derived from the 32-kHz clock and runs from 512 Hz down to 1 Hz. The 24V1 clock has a 4-bit divider from the 24M main oscillator, which allows it to run from 24 MHz down to 1.5 MHz. The 24V2 clock has a 4-bit divider from the 24V1 divider, which allows it to run from 24 MHz down to 93.7 kHz (based on both 24V1 and 24V2 values).

The CPU clock has an 8-bit divider derived from the 24-MHz main oscillator and can divide the source down to 93.7 kHz. The digital blocks can also produce ACLK0 and ACLK1 clock signals to be used by the analog blocks. These two clocks along with the 24V1 and 24V2 clocks are available to each of the four Acolumnx analog block multiplexers. These select one of the clocks and allow it to be further divided by a 4-bit divider for clocking any of the analog blocks (more on this a little later).

CPU Features

CY8C2xxx devices have several hardware features. The two’s compliment MAC provides immediate results. Writing 8-bit signed values to both MUL_X and MUL_Y will cause a multiply to occur and the result available as a 16-bit signed word in MUL_DH and MUL_DY. A multiply and accumulate begins when either the MAC_X or MAC_Y register is written to. The 32-bit signed double word result is available in registers ACC_DR0 through ACC_DR3.

Although the analog blocks include high-speed comparators, without a data decimator these comparators would be little more than 1-bit A/D converters. The decimator allows a high-speed 1-bit datastream to be converted to lower speed multiple bit data. When used in conjunction with the other PSoC blocks, this function can provide an n-bit ADC.

There are two types of reset for CY8C2xxx devices. Power-on reset (POR) takes place when VCC rises above the 2.3-VDC threshold. An external reset input (CY8C26xxx) will also force a POR. A POR provides a minimum of 864 µs for the VCC to complete its rise prior to executing any code at the reset vector. A watchdog reset (WDR, based on SLP) will also force a POR. Register CPU_SCR (0xFF in both register banks) holds status bits showing which function caused the reset.

Sleep mode reduces power consumption in one of two ways. When the stop bit is set in the CPU-SCR register, the main oscillator is halted. All functions associated with this clock or those derived from it cease.

To further reduce current, you can disable the analog block power by clearing the PWR bits in register ARF_CR (0x63 in bank 0). When the CPU is halted, only an interrupt, WDR, or POR will restart the processor. Although the stop bit is reset, allowing the CPU to operate, you must turn on the analog power. The low-speed oscillator continues to run unless you intentionally disable it.

Another hardware feature is an on-board Switch mode pump that creates a temporary working voltage higher than the rising VCC to allow the supply voltage monitor (SVM) circuitry to operate properly. One of eight programmable low-voltage trip levels can then initiate a POR if the VCC is lost or reduced for some reason. An internal band-gap reference source is used for the SVM and as an analog reference. Because the band-gap reference is sensitive to voltage, a trim register is provided to adjust compensations when a VCC other than 5 VDC is used.

The CPU has an on-board supervisor ROM to manage flash memory programming, erasure, and protection issues. The ROM has additional capabilities like reading product IDs and calculating flash memory block checksums. You can access these ROM routines with the system supervisor call instruction SSC. Various functions can be called based on the value in the accumulator (ACC). Certain functions require parameters to be preset into the upper eight RAM locations and any values returned are put in those same locations.