Issue 141 March 2002
You Too Can Design with SoC

A Design Challenge 2002 Primer

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PSoC

The Harvard architecture of this 8-bit core provides faster overall throughput because it has separate address and data buses. Although the processor can be clocked up to 24 MHz, slower clocks have the advantage of consuming less current. The instruction set has more than 130 instructions based on variants of less than 30, including bit manipulations. All devices have access to both analog and digital blocks from the smallest 8-pin device to the largest 48-pin device.

Each block can be used alone for simple functions or in combination with other blocks to produce higher level functions. An 8 × 8 hardware multiply and 32-bit accumulate module (MAC) presents results in a single instruction cycle. Every I/O pin can serve as an interrupt source and has highly configurable output drive specifications.

The main oscillator achieves ±2.5% accuracy without the use of a crystal. If higher accuracy is necessary, a 32-kHz clock crystal provides both low-speed oscillator accuracy and a PLL reference for the high-speed oscillator. The low-speed oscillator, which can run without a crystal, provides additional clocking for the watchdog/sleep timer and the PSoC blocks.

The flash memory has an endurance of more than 100,000 erase/write cycles and uses a flexible protection scheme to prevent not only unwanted writes but also unauthorized reads. Let’s take a brief look at some important points of the basic architecture before delving into the analog and digital blocks.

Core

The primary operation of the M8C core is controlled through six primary registers, which are not directly accessible. Although these registers are not mapped into either of the two register banks, they affect or are effected by various instructions either directly or indirectly.

Figure 2 shows the bit breakdown of the six CPU registers (CPU_F, CPU_A, CPU_X, CPU_SP, and CPU_PCH/PCL). Note: Although it isn’t shown in Figure 2, the upper three reserved bits will be used for RAM bank switching on devices that support more than 256 bytes of RAM.

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Figure 2—You cannot directly access these system registers.

The instruction set is broken down into five areas, program flow, nondestructive tests, arithmetic, movement, and logical manipulations. There are 10 possible addressing modes for instructions. Four modes affect the source register: Immediate, Direct, Indexed, and Indirect Post Increment. The source is the constant value during Immediate mode. RAM or the register location’s value is the source during Direct mode. For Indexed mode, an offset is added to RAM or a register’s location and the new location’s value is the source. For Indirect Post Increment mode, a pointer stored at a RAM location points to the source value; the pointer is incremented after the instruction is executed.

Three modes, Direct, Indexed, Indirect Post Increment, affect the destination register. Three additional modes affect both the source and destination and are combinations of the previous modes: Destination Direct Source Immediate, Destination Indexed Source Immediate, and Destination Direct Source Direct.

RAM, flash memory, and register banks serve as three separate memory spaces for the CY8C2xxx. The internal flash memory is a linear array, beginning with interrupt vectors at location 0x0000. User memory begins at 0x0040 and ends with the available memory up to 16 KB.

The internal RAM memory is 128 or 256 KB. The hardware stack builds up from low memory at 0x00 to a user-defined top of stack (TOS). General-purpose RAM extends from the TOS to the end of available RAM.

The register memory is divided into two register banks—zero and one. The bank is selected using XIO, bit 4 of the CPU_F non-addressable register. All peripheral registers, including those associated with the programmable analog and digital blocks, have a location set aside in at least one of the two register banks.

I/O

Refer to Figure 3 for the I/O port register configurations. The state of an output bit is set when output data is written to the data register. The logic state of an input pin is read through the same data register.

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Figure 3—Up to 44 bits of I/O are supported on CY8C2xxx devices. The flexibility of each I/O bit is visible though the seven registers used to configure each port. If these registers are implemented, port 5 is 4 bits wide.

The interrupt enable register allows every bit to be enabled as an interrupt source. The global select register allows the I/O pin to be routed to one of the global buses for use with the analog and digital blocks. The next pair of drive mode registers designates the pin configuration.

The state (logic 0 or 1) of each pin can be configured as High-Z, hard-driven, or resistive pull-up/down. Finally, the last pair of interrupt control registers configures any enabled interrupt pin for rising, falling, or change-of-state interrupt operation.