Start • Pipelined Execution • Memory Accesses • Branching Out • Interrupts • Control Unit Design • Decode Stage • The Execute Stage • PDF

THE EXECUTE STAGE

Now, let’s discuss the EX stage ALU, result mux, and address unit controls. The ALU and shift control outputs are:

• ADD: set unless the instruction is sub or sbc
• CI: carry-in. 0 for add and 1 for sub, unless it’s adc or sbc where we XOR in the previous carry-out
• LOGICOP1:0: select and, or, xor, or andn. LOGICOP1:0 is simply EXIR5:4 (i.e., EX stage copy of FN1:0)
• SRI: shift right input—0 for srli and A15 for srai (shift right arithmetic)

slxi and srxi (shift extended left/right for multi-word shift support) are not yet implemented. Be my guest!

The result mux control outputs SUMT, LOGICT, SLT, SRT, SXT, and RETADT are active low RESULT bus 3-state output enables. Each cycle, all EX stage function units produce results. One asserted T enables its unit’s 3-state buffers to drive the RESULT bus, as shown in Table 5.

Enable	Instruction	Source
SUMT	add sub addi adc sbc adci sbci	SUM15:0
LOGICT	and or xor andn andi ori xori andni	LOGIC15:0
SLT	slli	A14:0 || 0
SRT	srli srai	SRI || A15:1
ZXT	lb	015:8
RETADT	jal call	RETAD15:0
none	sw sb br* imm	—
Table 5—Here’s a look at the result multiplexer output enable controls.

The instruction determines which enable is asserted and which function unit drives RESULT15:0.

ZXT zeroes RESULT15:8 during lb. As you’ll see next month, the system drives RESULT7:0 with the byte load result.

The following outputs control the address unit:

• BRANCH: if set, add 2×disp8 to PC, otherwise add +2
• SELPC: if set, next address is PCNEXT15:0, otherwise SUM15:0
• ZEROPC: if set, next address is 0
• PCCE (PC clock enable): update PCi
• DMAPC: if set, fetch and update PC1 (DMA address), otherwise PC0 (PC)

Depending on the next memory cycle and the current EX stage instruction, the control unit selects the next address by asserting certain combinations of control outputs (see Table 6).

Next cycle	Next address	Outputs
IF	AN ¬ PC0 += 2	SELPC PCCE
IF branch	AN ¬ PC0 += 2´disp8	BRANCH SELPC PCCE
IFjal call	AN ¬ PC0 = SUM	PCCE
IFreset	AN ¬ PC0 = 0	SELPC ZEROPC PCCE
LS load/store	AN ¬ SUM	—
DMA	AN ¬ PC1 += 2	SELPC DMAPC PCCE
DMA reset	AN ¬ PC1 = 0	SELPC ZEROPC DMAPC PCCE
Table 6—Here’s a look at the result multiplexer output enable controls. The instruction determines which enable to assert and thus determines which function unit drives the RESULT bus.

WRAP-UP

This month, we considered pipelined processor design issues and explored the detailed
implementation of our xr16 control unit—and lived! The CPU design is complete. The final article in this series tackles the design of this System-on-a-Chip.

Jan Gray is a software developer whose products include a leading C++ compiler. He has been building FPGA processors and systems since 1994, and now he designs for Gray Research LLC. You may reach him at jan@fpgacpu.org.