Start • Pipelined Execution • Memory Accesses • Branching Out • Interrupts • Control Unit Design • Decode Stage • The Execute Stage • PDF

DECODE STAGE

The greater part of the control unit operates in the DC stage. It must decode the new instruction, control the register file, the A and B operand multiplexers, and prepare most EX stage control signals.

The instruction register IR latches the new instruction word as the DC stage begins. The buffers IRB and IMMB break out the instruction fields OP, RD, and so forth—IR15:12 is renamed OP3:0 and so on (the tools optimize away these buffers).

The instruction decoder DECODE is simple. It is a set of 30 ROM 16x1s, gate expressions, and a handful of flip-flops. Each ROM inputs OP3:0 or EXOP3:0 and outputs some decoded signal. The decoder is relatively compact because xr16 has a simple instruction set, and its 4-bit opcodes are a good match for the FPGA’s 4 LUTs.

The register file control signals, shared by both the DC and EX stages, are RNA3:0: port A register number; RNB3:0: port B register number; and RFWE: register file write enable.

With CLK high, CTRL drives RNA and RNB with the DC stage instruction’s source register numbers. With CLK low, CTRL drives RNA and RNB with the EX stage destination register number.

RFWE is asserted with PCE when there is a result to write back. It is false for instructions, which produces no result (immediate prefix, branch, or store) for annulled instructions, and for destination r0.

The muxes RNA and RNB produce RNA3:0 and RNB3:0, as shown in Table 4, as selected by decode outputs RRRI, CALL, ST, EXCALL, and CLK. Call is irregular. It computes r15 = pc, pc = r0 + imm12<<4, and the registers r15 and r0 are implicit.

RNA	When
RA	DC: add sub addi lw lb sw sb jal
RD	DC: all rr, ri format
0	DC: call
EXRD	EX: all but call
15	EX: call

RNB	When
RB	DC: add sub, all rr fmt
RD	DC: sw sb
EXRD	EX: all but call
15	EX: call
Table 4—RNA and RNB control the A and B ports of the register file. While CLK is high, they select which registers to read, based upon register fields of the instruction in the DC stage. While CLK is low, they select which register to write, based upon the instruction in the EX stage.

The FWD signal causes RESULT to be forwarded into A, overriding AREG. CTRL asserts FWD when the EX stage destination register equals the DC stage source register A (detected within RNA), unless the EX stage instruction is annulled or its destination is r0.

Last month, I discussed IMMED, the BREG/immediate operand mux. IMMOP5:0 controls IMMED, based upon the decoder outputs WORDIMM, SEXTIMM4, IMM_12, and IMM_4.

B3:0 is clock enabled on PCE, but B15:4 uses B15_4CE. B15_4CE is PCE, unless the EX stage instruction is imm. Thus, the imm prefix establishes B15:4, and the subsequent immediate operand instruction provides B3:0 only.

Now, turning to conditional branches, if the DC stage instruction is a branch, then the EX stage instruction must be add, sub, or addi, which drives the control unit’s condition inputs Z (zero), N (negative), CO (carry-out), and V (overflow).

Late in the DC stage, the TRUE macro evaluates whether or not the branch condition COND is true with respect to the condition inputs. If so, and if the branch instruction is not annulled, the BRANCH flip-flop is set. Therefore, as the pipeline advances and the branch instruction enters the EX stage, the BRANCH control output is asserted. This directs PCINCR to take the branch by adding 2×disp8 to the PC.