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CONTROL UNIT DESIGN

Now that you understand the pipeline, you are ready to design the control unit. (For more information on RISC pipelines, see Computer Organization and Design: The Hardware/Software Interface, by Patterson and Hennessy.) [1] First, some important naming conventions. Some control unit signal names have prefixes and suffixes to recognize their function or context (most signal names sans prefix are DC stage signals):

• Nsig: not signal—signal inverted
• DCsig: a DC stage signal
• EXsig: an EX stage signal
• sigN: signal in "next cycle"—input to a flip-flop whose output is sig
• sigCE: flip-flop clock enable
• sigT: active low 3-state buffer output enable

Each instruction flows through the three stages (IF, DC, and EX) of the control unit (see Figure 2) pipeline. In the IF stage, when the instruction fetch read completes, the new instruction at INSN15:0 is latched into IR.

Figure 2—This control unit schematic implements half of the symbol CTRL16 in last month’s Figure 2, including the CPU finite state machine, instruction register pipline, and instruction decoder. Instructions enter on INSN15:0 and are latched in IR and decoded.

In the DC stage, DECODE decodes IR to derive internal control signals. In the first half clock cycle, CTRL drives RNA3:0 and RNB3:0 with the source registers to read, and drives FWD and IMM5:0 to select the A and B operands. If the instruction is a branch, CTRL determines if it is taken. Then as the pipeline advances, the instruction passes into EXIR.

In the EX stage, CTRL drives ALU and result mux controls. If the instruction is a load/store, it inserts a memory access. In the last half cycle, RNA and RNB both drive the destination register number to store the result into the register file.

Let’s consider each part of the control finite state machine (see Figure 1). The control FSM has three states:

• IF: current memory access is an instruction fetch cycle
• DMA: current access is a DMA cycle
• LS: current access is a load/store

	Figure 1—This control unit finite state machine schematic implements the symbol CTRLFSM in Figure 2. It consists of the memory cycle FSM (see Figure 4), plus instruction annulment and pending request registers. The FSM outputs are derived from the machines current and next states.

Figure 4 shows the state transition diagram. The FSM clocks when one memory transaction completes and another begins (on RDY). CTRLFSM also has several other bits of state:

• DCANNUL: annul DC stage
• EXANNUL: annul EX stage
• DCINT: int in DC stage
• DMAP: DMA transfer pending
• INTP: interrupt pending

Figure 3—The remainder of the control unit schematic implements the DC stage operand selection logic including register file, immediate operand control, branch logic, EX stage ALU, and result mux controls.

DCANNUL and EXANNUL are set after executing a jump or taken branch. They suppress any effects of the two instructions in the branch shadow, including register file write-back and load/store memory accesses. So, an annulled add still fetches and adds its operands, but its results are not retired to the register file.

Figure 4—Each memory cycle is an instruction fetch unless there is a DMA transfer pending or the EX stage instruction is a load or store. The FSM clocks when one memory transaction completes and another begins (on RDY).

DCINT is set in the pipeline cycle following the insertion of the int instruction. It inhibits clocking of RET for one cycle, so that the int picks up the return address of the interrupted instruction rather than the instruction after that.

The highest fan-out control signal is PCE, the pipeline clock enable. Most datapath registers are enabled by PCE. It indicates that all pipe stages are ready and the pipeline can advance. PCE is asserted when RDY signals completion of the last memory cycle in the current pipeline cycle. If memory isn’t ready, PCE isn’t asserted, and the pipeline stalls for one cycle.

The control FSM also takes care of managing the memory interface via the following signals:

• RDY: memory cycle complete (input from the memory controller)
• READN: next memory cycle is a read transaction—true except for stores
• WORDN: next cycle is 16-bit data—true except for byte loads/stores
• DBUSN: next cycle is a load/store, and it needs the on-chip data bus
• ACE (address clock enable): the next address AN15:0 (a datapath output) and the above control outputs are all valid, so start a new memory transaction in the next clock cycle. ACE equals RDY, because if memory is ready, the CPU is always eager to start another memory transaction.

There are no IF stage control outputs. Internal to the control unit, three signals control IF stage resources. Those three signals are:

• PCE: enable IR and EXIR clocking
• IF: asserted in an instruction fetch memory cycle
• IFINT: force the next instruction to be int = jal r14,10(r0) = 0xAE01

If a DMA or load/store access is pending, IF enables NEXTIR to capture the previously fetched instruction (take a look back at time t3 in Table 3). Otherwise, the instruction fetch is the only memory access in the pipe stage. So, IF is then asserted with PCE, and IRMUX selects the INSN15:0 input as the next instruction to complete.