Start • Pipelined Execution • Memory Accesses • Branching Out • Interrupts • Control Unit Design • Decode Stage • The Execute Stage • PDF

BRANCHING OUT

Next, consider the effect of jumps (call and jal) and taken branches. By the time you execute the jump or taken branch IJ during EXJ (updating PC), you’ll have decoded IJ+1 and fetched IJ+2. These instructions in the branch shadow (and their side effects) must be annulled.

Continuing the Table 3 example from time t5, and assuming the branch is taken at t7, you must annul the EX5 stage of I5, and the DC6 and EX6 stages of I6. (Annulled stages are struck through). Execution continues at instruction IT. T9 is not an EX5 load cycle, because the I5 load is annulled.

Because you always annul the two branch shadow instructions, jumps and taken branches take three cycles. Jumps also save the return address in the destination register. This return address is obtained from the datapath’s RET register, which holds the address of the instruction in the DC pipeline stage.