state_diagram 	sreg;
state s0:
	when (phaseB==1 & phaseA==0) then (dir=1)
	else when (phaseB==0 & phaseA==1) then (dir=0)
	if (phaseB==1 & phaseA==0) then s2
	else if (phaseB==0 & phaseA==1 then s1
	else s=0
state s1:
	when (phaseB==0 & phaseA==0) then (dir=0)
	else when (phaseB==1 & phaseA==1) then (dir=0)
	if (phaseB==0 & phaseA==0) then s0
	else if (phaseB==1 & phaseA==1 then s3
	else s=1
state s2:
	when (phaseB==1 & phaseA==1) then (dir=1)
	else when (phaseB==0 & phaseA==0) then (dir=0)
	if (phaseB==1 & phaseA==1) then s3
	else if (phaseB==0 & phaseA==0 then s0
	else s=2
state s3:
	when (phaseB==0 & phaseA==1) then (dir=0)
	else when (phaseB==1 & phaseA==0) then (dir=0)
	if (phaseB==0 & phaseA==1) then s1
	else if (phaseB==1 & phaseA==0 then s2
	else s=3

Listing 1—Sometimes a state-table format is more appropriate, as in this example for an optical encoder.