March 1999, Issue 104

JTAG—Working with CoolPLD

SIMULATION

Once the .PHD file has all the proper information, the file can be compiled for a specific part. There are several options that simplify compilation (i.e., pin assignment). The compiled file can then be fitted into the part yielding a resource report (.FIT), a timing report (.TIM), and the jedec file (.JED) used to program the device.

The XPLA designer’s simulator provides a graphical logic-analyzer view of each input, internal node, feedback, and output signal. The inputs can be stimulated through an interactive waveform editor or vector file. Once the compiled design is fitted to a part, the simulator gives true timing characteristics based on the selected device.